[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 4/4] target/openrisc: Use dc->zero in gen_add, gen_addc
From: |
Richard Henderson |
Subject: |
[PATCH 4/4] target/openrisc: Use dc->zero in gen_add, gen_addc |
Date: |
Thu, 8 Jul 2021 14:37:54 -0700 |
We still need the t0 temporary for computing overflow,
but we do not need to initialize it to zero first.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/translate.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 3d86bdffaa..3425fd881e 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -200,10 +200,10 @@ static void gen_ove_cyov(DisasContext *dc)
static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
{
- TCGv t0 = tcg_const_tl(0);
+ TCGv t0 = tcg_temp_new();
TCGv res = tcg_temp_new();
- tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, srcb, t0);
+ tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, srcb, dc->zero);
tcg_gen_xor_tl(cpu_sr_ov, srca, srcb);
tcg_gen_xor_tl(t0, res, srcb);
tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov);
@@ -217,11 +217,11 @@ static void gen_add(DisasContext *dc, TCGv dest, TCGv
srca, TCGv srcb)
static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
{
- TCGv t0 = tcg_const_tl(0);
+ TCGv t0 = tcg_temp_new();
TCGv res = tcg_temp_new();
- tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, cpu_sr_cy, t0);
- tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, t0);
+ tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, cpu_sr_cy, dc->zero);
+ tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, dc->zero);
tcg_gen_xor_tl(cpu_sr_ov, srca, srcb);
tcg_gen_xor_tl(t0, res, srcb);
tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov);
--
2.25.1