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[Bug 1901359] Re: ignore bit 0 in pci CONFIG_ADDRESS register write for
Launchpad Bug Tracker
[Bug 1901359] Re: ignore bit 0 in pci CONFIG_ADDRESS register write for Type 1 access
Fri, 09 Jul 2021 04:17:26 -0000
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
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ignore bit 0 in pci CONFIG_ADDRESS register write for Type 1 access
Status in QEMU:
I'v recently stumbled upon a bug in the Plan9 PCI config space access
routines for config mode #1.
The code used to set bit 0 in the CONFIG_ADDRESS register for a Type 1
This was most likely a misreading of the PCI local bus specification
on our side.
However, in the PCI local bus specification 3.0, it states the
> 184.108.40.206.2 Software Generation of Configuration Transactions
> For Type 1 translations, the host bridge directly copies the contents of the
> CONFIG_ADDRESS register (excluding bits 31 and 0) onto the PCI AD lines
> address phase of a configuration transaction making sure that AD[1::0] is
note the: "excluding bits 31 and 0"
What happens in qemu instead is that it uses bit 0 of the CONFIG_ADDRESS
register as part of the register offset (when it probably should ignore it)
when translating from Type 1 to Type 0 address. So once it reaches the device
behind the bridge the register address is off by one.
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