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[PULL 17/17] hw/intc: Improve formatting of MEMTX_ERROR guest error mess
From: |
Peter Maydell |
Subject: |
[PULL 17/17] hw/intc: Improve formatting of MEMTX_ERROR guest error message |
Date: |
Fri, 9 Jul 2021 17:10:03 +0100 |
From: Rebecca Cran <rebecca@nuviainc.com>
Add a space in the message printed when gicr_read*/gicr_write* returns
MEMTX_ERROR in arm_gicv3_redist.c.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210706211432.31902-1-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_redist.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 8645220d618..53da703ed84 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -453,7 +453,7 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset,
uint64_t *data,
if (r == MEMTX_ERROR) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest read at offset " TARGET_FMT_plx
- "size %u\n", __func__, offset, size);
+ " size %u\n", __func__, offset, size);
trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,
size, attrs.secure);
/* The spec requires that reserved registers are RAZ/WI;
@@ -510,7 +510,7 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset,
uint64_t data,
if (r == MEMTX_ERROR) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid guest write at offset " TARGET_FMT_plx
- "size %u\n", __func__, offset, size);
+ " size %u\n", __func__, offset, size);
trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,
size, attrs.secure);
/* The spec requires that reserved registers are RAZ/WI;
--
2.20.1
- [PULL 02/17] stm32vldiscovery: Add the STM32VLDISCOVERY Machine, (continued)
- [PULL 02/17] stm32vldiscovery: Add the STM32VLDISCOVERY Machine, Peter Maydell, 2021/07/09
- [PULL 05/17] hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write, Peter Maydell, 2021/07/09
- [PULL 03/17] docs/system: arm: Add stm32 boards description, Peter Maydell, 2021/07/09
- [PULL 04/17] tests/boot-serial-test: Add STM32VLDISCOVERY board testcase, Peter Maydell, 2021/07/09
- [PULL 09/17] hw/gpio/pl061: Document the interface of this device, Peter Maydell, 2021/07/09
- [PULL 07/17] hw/gpio/pl061: Clean up read/write offset handling logic, Peter Maydell, 2021/07/09
- [PULL 06/17] hw/gpio/pl061: Convert DPRINTF to tracepoints, Peter Maydell, 2021/07/09
- [PULL 08/17] hw/gpio/pl061: Add tracepoints for register read and write, Peter Maydell, 2021/07/09
- [PULL 13/17] hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset, Peter Maydell, 2021/07/09
- [PULL 15/17] hw/arm/stellaris: Expand comment about handling of OLED chipselect, Peter Maydell, 2021/07/09
- [PULL 17/17] hw/intc: Improve formatting of MEMTX_ERROR guest error message,
Peter Maydell <=
- [PULL 10/17] hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers, Peter Maydell, 2021/07/09
- [PULL 16/17] target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint, Peter Maydell, 2021/07/09
- [PULL 11/17] hw/gpio/pl061: Make pullup/pulldown of outputs configurable, Peter Maydell, 2021/07/09
- [PULL 14/17] hw/gpio/pl061: Document a shortcoming in our implementation, Peter Maydell, 2021/07/09
- [PULL 12/17] hw/arm/virt: Make PL061 GPIO lines pulled low, not high, Peter Maydell, 2021/07/09
- Re: [PULL 00/17] target-arm queue, Peter Maydell, 2021/07/11