Re: [PATCH v1 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines

[Alistair Francis]

On Sat, Jul 10, 2021 at 1:36 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/8/21 8:30 PM, Alistair Francis wrote:
> > +typedef struct sifive_clint_callback {
> > +    SiFiveCLINTState *s;
> > +    int num;
> > +} sifive_clint_callback;
>
> Perhaps better to put "num", perhaps with a more descriptive name (hartid?), 
> into
> SiFiveCLINTState itself?

The problem is that there is a single SiFiveCLINTState because there
is a single CLINT, but we want to have a timer callback for each CPU
so we need something here that is per CPU.

>
> It would avoid some amount of double-indirection, and some awkward memory 
> allocation in
> sifive_clint_create.
>
>
> >           } else if ((addr & 0x3) == 0) {
> > -            riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MSIP, 
> > BOOL_TO_MASK(value));
> > +            if (value) {
> > +                qemu_irq_raise(clint->soft_irqs[hartid]);
> > +            } else {
> > +                qemu_irq_lower(clint->soft_irqs[hartid]);
> > +            }
>
> You should use qemu_irq_set here.

Will do!

Alistair

>
>
> r~