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Re: [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu |
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Date: |
Thu, 15 Jul 2021 15:02:18 +1000 |
On Fri, Jul 9, 2021 at 2:40 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Split out gen_mulh and gen_mulhu and use the common helper.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 16 ++++++++++++++++
> target/riscv/insn_trans/trans_rvm.c.inc | 24 ++----------------------
> 2 files changed, 18 insertions(+), 22 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 6ad40e43b0..8ff75a5798 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -235,6 +235,22 @@ static TCGv gpr_dst(DisasContext *ctx, int reg_num)
> return cpu_gpr[reg_num];
> }
>
> +static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
> +{
> + TCGv discard = tcg_temp_new();
> +
> + tcg_gen_muls2_tl(discard, ret, s1, s2);
> + tcg_temp_free(discard);
> +}
> +
> +static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
> +{
> + TCGv discard = tcg_temp_new();
> +
> + tcg_gen_mulu2_tl(discard, ret, s1, s2);
> + tcg_temp_free(discard);
> +}
> +
> static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
> {
> TCGv rl = tcg_temp_new();
> diff --git a/target/riscv/insn_trans/trans_rvm.c.inc
> b/target/riscv/insn_trans/trans_rvm.c.inc
> index 10ecc456fc..34220b824d 100644
> --- a/target/riscv/insn_trans/trans_rvm.c.inc
> +++ b/target/riscv/insn_trans/trans_rvm.c.inc
> @@ -28,17 +28,7 @@ static bool trans_mul(DisasContext *ctx, arg_mul *a)
> static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
> {
> REQUIRE_EXT(ctx, RVM);
> - TCGv source1 = tcg_temp_new();
> - TCGv source2 = tcg_temp_new();
> - gen_get_gpr(source1, a->rs1);
> - gen_get_gpr(source2, a->rs2);
> -
> - tcg_gen_muls2_tl(source2, source1, source1, source2);
> -
> - gen_set_gpr(a->rd, source1);
> - tcg_temp_free(source1);
> - tcg_temp_free(source2);
> - return true;
> + return gen_arith(ctx, a, gen_mulh);
> }
>
> static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
> @@ -50,17 +40,7 @@ static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
> static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
> {
> REQUIRE_EXT(ctx, RVM);
> - TCGv source1 = tcg_temp_new();
> - TCGv source2 = tcg_temp_new();
> - gen_get_gpr(source1, a->rs1);
> - gen_get_gpr(source2, a->rs2);
> -
> - tcg_gen_mulu2_tl(source2, source1, source1, source2);
> -
> - gen_set_gpr(a->rd, source1);
> - tcg_temp_free(source1);
> - tcg_temp_free(source2);
> - return true;
> + return gen_arith(ctx, a, gen_mulhu);
> }
>
> static bool trans_div(DisasContext *ctx, arg_div *a)
> --
> 2.25.1
>
>
- [PATCH 08/17] target/riscv: Use gpr_{src, dst} for word shift operations, (continued)
- [PATCH 08/17] target/riscv: Use gpr_{src, dst} for word shift operations, Richard Henderson, 2021/07/09
- [PATCH 09/17] target/riscv: Reorg csr instructions, Richard Henderson, 2021/07/09
- [PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB, Richard Henderson, 2021/07/09
- [PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF, Richard Henderson, 2021/07/09
- [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD, Richard Henderson, 2021/07/09
- [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu, Richard Henderson, 2021/07/09
- Re: [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu,
Alistair Francis <=
- [PATCH 17/17] target/riscv: Remove gen_get_gpr, Richard Henderson, 2021/07/09
- Re: [PATCH 00/17] target/riscv: Use tcg_constant_*, LIU Zhiwei, 2021/07/15