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[PATCH v4 09/33] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX
From: |
Yang Zhong |
Subject: |
[PATCH v4 09/33] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX |
Date: |
Mon, 19 Jul 2021 19:21:12 +0800 |
From: Sean Christopherson <sean.j.christopherson@intel.com>
CPUID leaf 12_1_EAX is an Intel-defined feature bits leaf enumerating
the platform's SGX capabilities that may be utilized by an enclave, e.g.
whether or not an enclave can gain access to the provision key.
Currently there are six capabilities:
- INIT: set when the enclave has has been initialized by EINIT. Cannot
be set by software, i.e. forced to zero in CPUID.
- DEBUG: permits a debugger to read/write into the enclave.
- MODE64BIT: the enclave runs in 64-bit mode
- PROVISIONKEY: grants has access to the provision key
- EINITTOKENKEY: grants access to the EINIT token key, i.e. the
enclave can generate EINIT tokens
- KSS: Key Separation and Sharing enabled for the enclave.
Note that the entirety of CPUID.0x12.0x1, i.e. all registers, enumerates
the allowed ATTRIBUTES (128 bits), but only bits 31:0 are directly
exposed to the user (via FEAT_12_1_EAX). Bits 63:32 are currently all
reserved and bits 127:64 correspond to the allowed XSAVE Feature Request
Mask, which is calculated based on other CPU features, e.g. XSAVE, MPX,
AVX, etc... and is not exposed to the user.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
target/i386/cpu.c | 21 +++++++++++++++++++++
target/i386/cpu.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0525a4cf7f..840f825431 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -655,6 +655,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
#define TCG_14_0_ECX_FEATURES 0
#define TCG_SGX_12_0_EAX_FEATURES 0
#define TCG_SGX_12_0_EBX_FEATURES 0
+#define TCG_SGX_12_1_EAX_FEATURES 0
FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_1_EDX] = {
@@ -1222,6 +1223,26 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.tcg_features = TCG_SGX_12_0_EBX_FEATURES,
},
+
+ [FEAT_SGX_12_1_EAX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ NULL, "sgx-debug", "sgx-mode64", NULL,
+ "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 0x12,
+ .needs_ecx = true, .ecx = 1,
+ .reg = R_EAX,
+ },
+ .tcg_features = TCG_SGX_12_1_EAX_FEATURES,
+ },
};
typedef struct FeatureMask {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a71d1c8fd0..e4d46cca80 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -563,6 +563,7 @@ typedef enum FeatureWord {
FEAT_14_0_ECX,
FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
+ FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
FEATURE_WORDS,
} FeatureWord;
- [PATCH v4 00/33] Qemu SGX virtualization, Yang Zhong, 2021/07/19
- [PATCH v4 01/33] memory: Add RAM_PROTECTED flag to skip IOMMU mappings, Yang Zhong, 2021/07/19
- [PATCH v4 03/33] qom: Add memory-backend-epc ObjectOptions support, Yang Zhong, 2021/07/19
- [PATCH v4 02/33] hostmem: Add hostmem-epc as a backend for SGX EPC, Yang Zhong, 2021/07/19
- [PATCH v4 04/33] i386: Add 'sgx-epc' device to expose EPC sections to guest, Yang Zhong, 2021/07/19
- [PATCH v4 05/33] vl: Add sgx compound properties to expose SGX EPC sections to guest, Yang Zhong, 2021/07/19
- [PATCH v4 06/33] i386: Add primary SGX CPUID and MSR defines, Yang Zhong, 2021/07/19
- [PATCH v4 07/33] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX, Yang Zhong, 2021/07/19
- [PATCH v4 08/33] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX, Yang Zhong, 2021/07/19
- [PATCH v4 09/33] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX,
Yang Zhong <=
- [PATCH v4 10/33] i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs, Yang Zhong, 2021/07/19
- [PATCH v4 11/33] i386: Add feature control MSR dependency when SGX is enabled, Yang Zhong, 2021/07/19
- [PATCH v4 12/33] i386: Update SGX CPUID info according to hardware/KVM/user input, Yang Zhong, 2021/07/19
- [PATCH v4 13/33] i386: kvm: Add support for exposing PROVISIONKEY to guest, Yang Zhong, 2021/07/19
- [PATCH v4 14/33] i386: Propagate SGX CPUID sub-leafs to KVM, Yang Zhong, 2021/07/19
- [PATCH v4 15/33] Adjust min CPUID level to 0x12 when SGX is enabled, Yang Zhong, 2021/07/19
- [PATCH v4 16/33] hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly, Yang Zhong, 2021/07/19
- [PATCH v4 17/33] hw/i386/pc: Account for SGX EPC sections when calculating device memory, Yang Zhong, 2021/07/19
- [PATCH v4 18/33] i386/pc: Add e820 entry for SGX EPC section(s), Yang Zhong, 2021/07/19
- [PATCH v4 19/33] i386: acpi: Add SGX EPC entry to ACPI tables, Yang Zhong, 2021/07/19