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Re: [PATCH v5 07/10] ACPI ERST: trace support


From: Igor Mammedov
Subject: Re: [PATCH v5 07/10] ACPI ERST: trace support
Date: Tue, 20 Jul 2021 15:15:09 +0200

On Wed, 30 Jun 2021 15:07:18 -0400
Eric DeVolder <eric.devolder@oracle.com> wrote:

> Provide the definitions needed to support tracing in ACPI ERST.
trace points should be introduced in patches that use them for the first time,
as it stands now series breaks bisection.

> 
> Signed-off-by: Eric DeVolder <eric.devolder@oracle.com>
> ---
>  hw/acpi/trace-events | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/hw/acpi/trace-events b/hw/acpi/trace-events
> index dcc1438..a5c2755 100644
> --- a/hw/acpi/trace-events
> +++ b/hw/acpi/trace-events
> @@ -55,3 +55,17 @@ piix4_gpe_writeb(uint64_t addr, unsigned width, uint64_t 
> val) "addr: 0x%" PRIx64
>  # tco.c
>  tco_timer_reload(int ticks, int msec) "ticks=%d (%d ms)"
>  tco_timer_expired(int timeouts_no, bool strap, bool no_reboot) 
> "timeouts_no=%d no_reboot=%d/%d"
> +
> +# erst.c
> +acpi_erst_reg_write(uint64_t addr, uint64_t val, unsigned size) "addr: 
> 0x%04" PRIx64 " <== 0x%016" PRIx64 " (size: %u)"
> +acpi_erst_reg_read(uint64_t addr, uint64_t val, unsigned size) " addr: 
> 0x%04" PRIx64 " ==> 0x%016" PRIx64 " (size: %u)"
> +acpi_erst_mem_write(uint64_t addr, uint64_t val, unsigned size) "addr: 
> 0x%06" PRIx64 " <== 0x%016" PRIx64 " (size: %u)"
> +acpi_erst_mem_read(uint64_t addr, uint64_t val, unsigned size) " addr: 
> 0x%06" PRIx64 " ==> 0x%016" PRIx64 " (size: %u)"
> +acpi_erst_pci_bar_0(uint64_t addr) "BAR0: 0x%016" PRIx64
> +acpi_erst_pci_bar_1(uint64_t addr) "BAR1: 0x%016" PRIx64
> +acpi_erst_realizefn_in(void)
> +acpi_erst_realizefn_out(unsigned size) "total nvram size %u bytes"
> +acpi_erst_reset_in(unsigned record_count) "record_count %u"
> +acpi_erst_reset_out(unsigned record_count) "record_count %u"
> +acpi_erst_class_init_in(void)
> +acpi_erst_class_init_out(void)




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