[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2 09/22] target/loongarch: Add fixed point bit instruction t
From: |
Song Gao |
Subject: |
Re: [PATCH v2 09/22] target/loongarch: Add fixed point bit instruction translation |
Date: |
Thu, 22 Jul 2021 16:17:55 +0800 |
User-agent: |
Mozilla/5.0 (X11; Linux mips64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 |
Hi, Philippe
On 07/22/2021 01:46 AM, Philippe Mathieu-Daudé wrote:
> On 7/21/21 11:53 AM, Song Gao wrote:
>> This patch implement fixed point bit instruction translation.
>>
>> This includes:
>> - EXT.W.{B/H}
>> - CL{O/Z}.{W/D}, CT{O/Z}.{W/D}
>> - BYTEPICK.{W/D}
>> - REVB.{2H/4H/2W/D}
>> - REVH.{2W/D}
>> - BITREV.{4B/8B}, BITREV.{W/D}
>> - BSTRINS.{W/D}, BSTRPICK.{W/D}
>> - MASKEQZ, MASKNEZ
>>
>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>> ---
>> target/loongarch/helper.h | 10 +
>> target/loongarch/insns.decode | 45 +++
>> target/loongarch/op_helper.c | 119 ++++++++
>> target/loongarch/trans.inc.c | 665
>> ++++++++++++++++++++++++++++++++++++++++++
>> 4 files changed, 839 insertions(+)
>
>> diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
>> index b2cbdd7..07c3d52 100644
>> --- a/target/loongarch/op_helper.c
>> +++ b/target/loongarch/op_helper.c
>> @@ -25,3 +25,122 @@ void helper_raise_exception(CPULoongArchState *env,
>> uint32_t exception)
>> {
>> do_raise_exception(env, exception, GETPC());
>> }
>> +
>> +target_ulong helper_cto_w(CPULoongArchState *env, target_ulong rj)
>> +{
>> + uint32_t v = (uint32_t)rj;
>> + int temp = 0;
>> +
>> + while ((v & 0x1) == 1) {
>> + temp++;
>> + v = v >> 1;
>> + }
>
> Why not use cto32() from "qemu/host-utils.h"
>>> +
>> + return (target_ulong)temp;
>> +}
>> +
>> +target_ulong helper_ctz_w(CPULoongArchState *env, target_ulong rj)
>> +{
>> + uint32_t v = (uint32_t)rj;
>> +
>> + if (v == 0) {
>> + return 32;
>> + }
>> +
>> + int temp = 0;
>> + while ((v & 0x1) == 0) {
>> + temp++;
>> + v = v >> 1;
>> + }
>
> ctz32
>
>> +
>> + return (target_ulong)temp;
>> +}
>> +
>> +target_ulong helper_cto_d(CPULoongArchState *env, target_ulong rj)
>> +{
>> + uint64_t v = rj;
>> + int temp = 0;
>> +
>> + while ((v & 0x1) == 1) {
>> + temp++;
>> + v = v >> 1;
>> + }
>
> cto64
>
>> +
>> + return (target_ulong)temp;
>> +}
>> +
>> +target_ulong helper_ctz_d(CPULoongArchState *env, target_ulong rj)
>> +{
>> + uint64_t v = rj;
>> +
>> + if (v == 0) {
>> + return 64;
>> + }
>> +
>> + int temp = 0;
>> + while ((v & 0x1) == 0) {
>> + temp++;
>> + v = v >> 1;
>> + }
>
> and ctz64?
>
Yes, I didn't notice the file "qemu/host-utils.h" before, thanks for kindly
help!
>> +
>> + return (target_ulong)temp;
>> +}
>> +
>> +target_ulong helper_bitrev_w(CPULoongArchState *env, target_ulong rj)
>> +{
>> + int32_t v = (int32_t)rj;
>> + const int SIZE = 32;
>> + uint8_t bytes[SIZE];
>> +
>> + int i;
>> + for (i = 0; i < SIZE; i++) {
>> + bytes[i] = v & 0x1;
>> + v = v >> 1;
>> + }
>> + /* v == 0 */
>> + for (i = 0; i < SIZE; i++) {
>> + v = v | ((uint32_t)bytes[i] << (SIZE - 1 - i));
>> + }
>> +
>> + return (target_ulong)(int32_t)v;
>> +}
>> +
>> +target_ulong helper_bitrev_d(CPULoongArchState *env, target_ulong rj)
>> +{
>> + uint64_t v = rj;
>> + const int SIZE = 64;
>> + uint8_t bytes[SIZE];
>> +
>> + int i;
>> + for (i = 0; i < SIZE; i++) {
>> + bytes[i] = v & 0x1;
>> + v = v >> 1;
>> + }
>> + /* v == 0 */
>> + for (i = 0; i < SIZE; i++) {
>> + v = v | ((uint64_t)bytes[i] << (SIZE - 1 - i));
>> + }
>> +
>> + return (target_ulong)v;
>> +}
>> +
>> +static inline target_ulong bitswap(target_ulong v)
>> +{
>> + v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
>> + ((v & (target_ulong)0x5555555555555555ULL) << 1);
>> + v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
>> + ((v & (target_ulong)0x3333333333333333ULL) << 2);
>> + v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
>> + ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
>> + return v;
>
> Is this revbit64?
>
No, helper_bitrev_d is revbit64(LoongArch insn is 'bitrev.d rd, rj').
bitswap function for 'bitrev.4b/8b rd, rj' instruction.
BITREV.4B:
bstr32[31:24] = BITREV(GR[rj][31:24])
bstr32[23:16] = BITREV(GR[rj][23:16])
bstr32[15: 8] = BITREV(GR[rj][15: 8])
bstr32[ 7: 0] = BITREV(GR[rj][ 7: 0])
GR[rd] = SignExtend(bstr32, GRLEN)
BITREV.8B:
GR[rd][63:56] = BITREV(GR[rj][63:56])
GR[rd][55:48] = BITREV(GR[rj][55:48])
GR[rd][47:40] = BITREV(GR[rj][47:40])
GR[rd][39:32] = BITREV(GR[rj][39:32])
GR[rd][31:24] = BITREV(GR[rj][31:24])
GR[rd][23:16] = BITREV(GR[rj][23:16])
GR[rd][15: 8] = BITREV(GR[rj][15: 8])
GR[rd][ 7: 0] = BITREV(GR[rj][ 7: 0])
We can see a detailed introduction in [1] 2.2.3.6.
[1] :
https://github.com/loongson/LoongArch-Documentation/releases/download/LoongArch-Vol1-v3/LoongArch-Vol1-v1.00-EN.pdf
Thanks
Song Gao
- Re: [PATCH v2 07/22] target/loongarch: Add fixed point arithmetic instruction translation, (continued)
Re: [PATCH v2 07/22] target/loongarch: Add fixed point arithmetic instruction translation, Richard Henderson, 2021/07/22
[PATCH v2 08/22] target/loongarch: Add fixed point shift instruction translation, Song Gao, 2021/07/21
[PATCH v2 09/22] target/loongarch: Add fixed point bit instruction translation, Song Gao, 2021/07/21
[PATCH v2 10/22] target/loongarch: Add fixed point load/store instruction translation, Song Gao, 2021/07/21
[PATCH v2 11/22] target/loongarch: Add fixed point atomic instruction translation, Song Gao, 2021/07/21
[PATCH v2 12/22] target/loongarch: Add fixed point extra instruction translation, Song Gao, 2021/07/21