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Re: [PATCH for-6.1 1/6] target/arm: Enforce that M-profile SP low 2 bits

From: Richard Henderson
Subject: Re: [PATCH for-6.1 1/6] target/arm: Enforce that M-profile SP low 2 bits are always zero
Date: Sun, 25 Jul 2021 08:14:46 -1000
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0

On 7/23/21 6:21 AM, Peter Maydell wrote:
For M-profile, unlike A-profile, the low 2 bits of SP are defined to be
RES0H, which is to say that they must be hardwired to zero so that
guest attempts to write non-zero values to them are ignored.

Implement this behaviour by masking out the low bits:
  * for writes to r13 by the gdbstub
  * for writes to any of the various flavours of SP via MSR
  * for writes to r13 via store_reg() in generated code

Note that all the direct uses of cpu_R[] in translate.c are in places
where the register is definitely not r13 (usually because that has
been checked for as an UNDEFINED or UNPREDICTABLE case and handled as

All the other writes to regs[13] in C code are either:
  * A-profile only code
  * writes of values we can guarantee to be aligned, such as
    - writes of previous-SP-value plus or minus a 4-aligned constant
    - writes of the value in an SP limit register (which we already
      enforce to be aligned)

Signed-off-by: Peter Maydell<peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


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