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[PATCH for-6.2 18/53] target/arm: Implement MVE VMLAS
From: |
Peter Maydell |
Subject: |
[PATCH for-6.2 18/53] target/arm: Implement MVE VMLAS |
Date: |
Thu, 29 Jul 2021 12:14:37 +0100 |
Implement the MVE VMLAS insn, which multiplies a vector by a vector
and adds a scalar.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
changes: don't decode U bit as it does not affect output values
---
target/arm/helper-mve.h | 4 ++++
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c | 26 ++++++++++++++++++++++++++
target/arm/translate-mve.c | 1 +
4 files changed, 34 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 16c4c3b8f61..715b1bbd012 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -347,6 +347,10 @@ DEF_HELPER_FLAGS_4(mve_vqdmullb_scalarw, TCG_CALL_NO_WG,
void, env, ptr, ptr, i3
DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr,
i32)
DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr,
i32)
+DEF_HELPER_FLAGS_4(mve_vmlasb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmlash, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmlasw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 4bd20a9a319..226b74790b3 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -345,6 +345,9 @@ VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110
.... @2scalar
VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
+# The U bit (28) is don't-care because it does not affect the result
+VMLAS 111- 1110 0 . .. ... 1 ... 1 1110 . 100 .... @2scalar
+
# Vector add across vector
{
VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0
rda=%rdalo
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 03171766b57..ab02a1e60f4 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -948,6 +948,22 @@ DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1,
do_vqdmlsdh_w)
mve_advance_vpt(env); \
}
+/* "accumulating" version where FN takes d as well as n and m */
+#define DO_2OP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \
+ uint32_t rm) \
+ { \
+ TYPE *d = vd, *n = vn; \
+ TYPE m = rm; \
+ uint16_t mask = mve_element_mask(env); \
+ unsigned e; \
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
+ mergemask(&d[H##ESIZE(e)], \
+ FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m), mask); \
+ } \
+ mve_advance_vpt(env); \
+ }
+
/* provide unsigned 2-op scalar helpers for all sizes */
#define DO_2OP_SCALAR_U(OP, FN) \
DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \
@@ -958,6 +974,11 @@ DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1,
do_vqdmlsdh_w)
DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \
DO_2OP_SCALAR(OP##w, 4, int32_t, FN)
+#define DO_2OP_ACC_SCALAR_U(OP, FN) \
+ DO_2OP_ACC_SCALAR(OP##b, 1, uint8_t, FN) \
+ DO_2OP_ACC_SCALAR(OP##h, 2, uint16_t, FN) \
+ DO_2OP_ACC_SCALAR(OP##w, 4, uint32_t, FN)
+
DO_2OP_SCALAR_U(vadd_scalar, DO_ADD)
DO_2OP_SCALAR_U(vsub_scalar, DO_SUB)
DO_2OP_SCALAR_U(vmul_scalar, DO_MUL)
@@ -987,6 +1008,11 @@ DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t,
DO_QRDMULH_B)
DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H)
DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W)
+/* Vector by vector plus scalar */
+#define DO_VMLAS(D, N, M) ((N) * (D) + (M))
+
+DO_2OP_ACC_SCALAR_U(vmlas, DO_VMLAS)
+
/*
* Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the
* input (smaller) type and LESIZE, LTYPE, LH for the output (long) type.
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index aa38218e08f..b56c91db2ab 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -596,6 +596,7 @@ DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar)
DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar)
DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar)
DO_2OP_SCALAR(VBRSR, vbrsr)
+DO_2OP_SCALAR(VMLAS, vmlas)
static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a)
{
--
2.20.1
- [PATCH for-6.2 09/53] target/arm: Factor out mve_eci_mask(), (continued)
- [PATCH for-6.2 09/53] target/arm: Factor out mve_eci_mask(), Peter Maydell, 2021/07/29
- [PATCH for-6.2 07/53] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts, Peter Maydell, 2021/07/29
- [PATCH for-6.2 08/53] target/arm: Fix calculation of LTP mask when LR is 0, Peter Maydell, 2021/07/29
- [PATCH for-6.2 10/53] target/arm: Fix VPT advance when ECI is non-zero, Peter Maydell, 2021/07/29
- [PATCH for-6.2 12/53] target/arm: Implement MVE VMULL (polynomial), Peter Maydell, 2021/07/29
- [PATCH for-6.2 13/53] target/arm: Implement MVE incrementing/decrementing dup insns, Peter Maydell, 2021/07/29
- [PATCH for-6.2 11/53] target/arm: Fix VLDRB/H/W for predicated elements, Peter Maydell, 2021/07/29
- [PATCH for-6.2 17/53] target/arm: Implement MVE VPSEL, Peter Maydell, 2021/07/29
- [PATCH for-6.2 18/53] target/arm: Implement MVE VMLAS,
Peter Maydell <=
- [PATCH for-6.2 15/53] target/arm: Implement MVE integer vector comparisons, Peter Maydell, 2021/07/29
- [PATCH for-6.2 14/53] target/arm: Factor out gen_vpst(), Peter Maydell, 2021/07/29
- [PATCH for-6.2 16/53] target/arm: Implement MVE integer vector-vs-scalar comparisons, Peter Maydell, 2021/07/29
- [PATCH for-6.2 21/53] target/arm: Implement MVE integer min/max across vector, Peter Maydell, 2021/07/29
- [PATCH for-6.2 20/53] target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats, Peter Maydell, 2021/07/29
- [PATCH for-6.2 23/53] target/arm: Implement MVE narrowing moves, Peter Maydell, 2021/07/29
- [PATCH for-6.2 30/53] target/arm: Implement MVE VMOV to/from 2 general-purpose registers, Peter Maydell, 2021/07/29
- [PATCH for-6.2 26/53] target/arm: Implement MVE VMLA, Peter Maydell, 2021/07/29