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[PATCH v3 66/66] tcg/riscv: Remove add with zero on user-only memory acc
From: |
Richard Henderson |
Subject: |
[PATCH v3 66/66] tcg/riscv: Remove add with zero on user-only memory access |
Date: |
Wed, 18 Aug 2021 09:19:20 -1000 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.c.inc | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index f75dcf88f8..b84a4e876b 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1182,9 +1182,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, bool is_64)
if (a_bits) {
tcg_out_test_alignment(s, true, addr_regl, a_bits);
}
- if (guest_base == 0) {
- tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
- } else {
+ if (guest_base != 0) {
tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
@@ -1256,9 +1254,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args, bool is_64)
if (a_bits) {
tcg_out_test_alignment(s, false, addr_regl, a_bits);
}
- if (guest_base == 0) {
- tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
- } else {
+ if (guest_base != 0) {
tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
--
2.25.1
- [PATCH v3 61/66] tcg/ppc: Support raising sigbus for user-only, (continued)
[PATCH v3 64/66] tcg: Canonicalize alignment flags in MemOp, Richard Henderson, 2021/08/18
[PATCH v3 65/66] tcg/riscv: Support raising sigbus for user-only, Richard Henderson, 2021/08/18
[PATCH v3 66/66] tcg/riscv: Remove add with zero on user-only memory access,
Richard Henderson <=