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[PATCH v3 10/16] tcg/mips: Create and use TCG_REG_TB
From: |
Richard Henderson |
Subject: |
[PATCH v3 10/16] tcg/mips: Create and use TCG_REG_TB |
Date: |
Wed, 18 Aug 2021 10:19:25 -1000 |
This vastly reduces the size of code generated for 64-bit addresses.
The code for exit_tb, for instance, where we load a (tagged) pointer
to the current TB, goes from
0x400aa9725c: li v0,64
0x400aa97260: dsll v0,v0,0x10
0x400aa97264: ori v0,v0,0xaa9
0x400aa97268: dsll v0,v0,0x10
0x400aa9726c: j 0x400aa9703c
0x400aa97270: ori v0,v0,0x7083
to
0x400aa97240: j 0x400aa97040
0x400aa97244: daddiu v0,s6,-189
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 73 ++++++++++++++++++++++++++++++++-------
1 file changed, 61 insertions(+), 12 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 1c5c0854c7..333b9572d0 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -88,6 +88,11 @@ static const char * const
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#ifndef CONFIG_SOFTMMU
#define TCG_GUEST_BASE_REG TCG_REG_S7
#endif
+#if TCG_TARGET_REG_BITS == 64
+#define TCG_REG_TB TCG_REG_S6
+#else
+#define TCG_REG_TB (qemu_build_not_reached(), TCG_REG_ZERO)
+#endif
/* check if we really need so many registers :P */
static const int tcg_target_reg_alloc_order[] = {
@@ -1961,34 +1966,72 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
switch (opc) {
case INDEX_op_exit_tb:
{
- TCGReg b0 = TCG_REG_ZERO;
+ TCGReg base = TCG_REG_ZERO;
+ int16_t lo = 0;
- a0 = (intptr_t)a0;
- if (a0 & ~0xffff) {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
- b0 = TCG_REG_V0;
+ if (a0) {
+ intptr_t ofs;
+ if (TCG_TARGET_REG_BITS == 64) {
+ ofs = tcg_tbrel_diff(s, (void *)a0);
+ lo = ofs;
+ if (ofs == lo) {
+ base = TCG_REG_TB;
+ } else {
+ base = TCG_REG_V0;
+ tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB);
+ }
+ } else {
+ ofs = a0;
+ lo = ofs;
+ base = TCG_REG_V0;
+ tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo);
+ }
}
if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0,
(uintptr_t)tb_ret_addr);
tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
}
- tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff);
+ tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo);
}
break;
case INDEX_op_goto_tb:
/* indirect jump method */
tcg_debug_assert(s->tb_jmp_insn_offset == 0);
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
- (uintptr_t)(s->tb_jmp_target_addr + a0));
- tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
- tcg_out_nop(s);
- set_jmp_reset_offset(s, a0);
+ {
+ TCGReg base, dest;
+ intptr_t ofs;
+
+ if (TCG_TARGET_REG_BITS == 64) {
+ dest = base = TCG_REG_TB;
+ ofs = tcg_tbrel_diff(s, s->tb_jmp_target_addr + a0);
+ } else {
+ dest = TCG_TMP0;
+ base = TCG_REG_ZERO;
+ ofs = (intptr_t)(s->tb_jmp_target_addr + a0);
+ }
+ tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs);
+ tcg_out_opc_reg(s, OPC_JR, 0, dest, 0);
+ /* delay slot */
+ tcg_out_nop(s);
+
+ set_jmp_reset_offset(s, args[0]);
+ if (TCG_TARGET_REG_BITS == 64) {
+ /* For the unlinked case, need to reset TCG_REG_TB. */
+ tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB,
+ -tcg_current_code_size(s));
+ }
+ }
break;
case INDEX_op_goto_ptr:
/* jmp to the given host address (could be epilogue) */
tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
- tcg_out_nop(s);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
+ } else {
+ tcg_out_nop(s);
+ }
break;
case INDEX_op_br:
tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
@@ -2672,6 +2715,9 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
}
#endif
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
+ }
/* Call generated code */
tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
@@ -2853,6 +2899,9 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */
+ }
}
typedef struct {
--
2.25.1
- [PATCH v3 04/16] tcg/mips: Move TCG_AREG0 to S8, (continued)
- [PATCH v3 04/16] tcg/mips: Move TCG_AREG0 to S8, Richard Henderson, 2021/08/18
- [PATCH v3 07/16] tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr, Richard Henderson, 2021/08/18
- [PATCH v3 05/16] tcg/mips: Move TCG_GUEST_BASE_REG to S7, Richard Henderson, 2021/08/18
- [PATCH v3 11/16] tcg/mips: Split out tcg_out_movi_one, Richard Henderson, 2021/08/18
- [PATCH v3 03/16] tcg/mips: Drop inline markers, Richard Henderson, 2021/08/18
- [PATCH v3 09/16] tcg/mips: Drop special alignment for code_gen_buffer, Richard Henderson, 2021/08/18
- [PATCH v3 10/16] tcg/mips: Create and use TCG_REG_TB,
Richard Henderson <=
- [PATCH v3 15/16] tcg/mips: Try tb-relative addresses in tcg_out_movi, Richard Henderson, 2021/08/18
- [PATCH v3 12/16] tcg/mips: Split out tcg_out_movi_two, Richard Henderson, 2021/08/18
- [PATCH v3 14/16] tcg/mips: Aggressively use the constant pool for n64 calls, Richard Henderson, 2021/08/18
- [PATCH v3 13/16] tcg/mips: Use the constant pool for 64-bit constants, Richard Henderson, 2021/08/18
- [PATCH v3 16/16] tcg/mips: Try three insns with shift and add in tcg_out_movi, Richard Henderson, 2021/08/18
- Re: [PATCH v3 00/16] tcg/mips: Unaligned access and other cleanup, Philippe Mathieu-Daudé, 2021/08/18