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[PATCH v3 07/14] tcg/arm: Split out tcg_out_ldstm
From: |
Richard Henderson |
Subject: |
[PATCH v3 07/14] tcg/arm: Split out tcg_out_ldstm |
Date: |
Wed, 18 Aug 2021 11:29:05 -1000 |
Expand these hard-coded instructions symbolically.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.c.inc | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index c55167cc84..63b786a3e5 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -134,6 +134,9 @@ typedef enum {
INSN_CLZ = 0x016f0f10,
INSN_RBIT = 0x06ff0f30,
+ INSN_LDMIA = 0x08b00000,
+ INSN_STMDB = 0x09200000,
+
INSN_LDR_IMM = 0x04100000,
INSN_LDR_REG = 0x06100000,
INSN_STR_IMM = 0x04000000,
@@ -586,6 +589,12 @@ static inline void tcg_out_dat_imm(TCGContext *s,
(rn << 16) | (rd << 12) | im);
}
+static void tcg_out_ldstm(TCGContext *s, int cond, int opc,
+ TCGReg rn, uint16_t mask)
+{
+ tcg_out32(s, (cond << 28) | opc | (rn << 16) | mask);
+}
+
/* Note that this routine is used for both LDR and LDRH formats, so we do
not wish to include an immediate shift at this point. */
static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg rt,
@@ -3119,7 +3128,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
{
/* Calling convention requires us to save r4-r11 and lr. */
/* stmdb sp!, { r4 - r11, lr } */
- tcg_out32(s, (COND_AL << 28) | 0x092d4ff0);
+ tcg_out_ldstm(s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK,
+ (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) |
+ (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) |
+ (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 <<
TCG_REG_R14));
/* Reserve callee argument and tcg temp space. */
tcg_out_dat_rI(s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK,
@@ -3147,7 +3159,10 @@ static void tcg_out_epilogue(TCGContext *s)
TCG_REG_CALL_STACK, STACK_ADDEND, 1);
/* ldmia sp!, { r4 - r11, pc } */
- tcg_out32(s, (COND_AL << 28) | 0x08bd8ff0);
+ tcg_out_ldstm(s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK,
+ (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) |
+ (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) |
+ (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC));
}
typedef struct {
--
2.25.1
- Re: [PATCH v3 01/14] tcg/arm: Remove fallback definition of __ARM_ARCH, (continued)
- [PATCH v3 03/14] tcg/arm: Simplify use_armvt5_instructions, Richard Henderson, 2021/08/18
- [PATCH v3 04/14] tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call, Richard Henderson, 2021/08/18
- [PATCH v3 05/14] tcg/arm: Examine QEMU_TCG_DEBUG environment variable, Richard Henderson, 2021/08/18
- [PATCH v3 06/14] tcg/arm: Support unaligned access for softmmu, Richard Henderson, 2021/08/18
- [PATCH v3 07/14] tcg/arm: Split out tcg_out_ldstm,
Richard Henderson <=
- [PATCH v3 02/14] tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}, Richard Henderson, 2021/08/18
- [PATCH v3 08/14] tcg/arm: Simplify usage of encode_imm, Richard Henderson, 2021/08/18
- [PATCH v3 09/14] tcg/arm: Drop inline markers, Richard Henderson, 2021/08/18
- [PATCH v3 10/14] tcg/arm: Give enum arm_cond_code_e a typedef and use it, Richard Henderson, 2021/08/18