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[PATCH v3 06/21] target/riscv: Remove gen_arith_div*
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From: |
Richard Henderson |
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Subject: |
[PATCH v3 06/21] target/riscv: Remove gen_arith_div* |
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Date: |
Wed, 18 Aug 2021 23:04:47 -1000 |
Use ctx->w and the enhanced gen_arith function.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 42 -------------------------
target/riscv/insn_trans/trans_rvm.c.inc | 16 +++++-----
2 files changed, 8 insertions(+), 50 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d862d0d0dd..bc40b9c701 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -495,48 +495,6 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
DisasExtend ext,
return true;
}
-static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
- void(*func)(TCGv, TCGv, TCGv))
-{
- TCGv source1, source2;
- source1 = tcg_temp_new();
- source2 = tcg_temp_new();
-
- gen_get_gpr(ctx, source1, a->rs1);
- gen_get_gpr(ctx, source2, a->rs2);
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_ext32s_tl(source2, source2);
-
- (*func)(source1, source1, source2);
-
- tcg_gen_ext32s_tl(source1, source1);
- gen_set_gpr(ctx, a->rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
- return true;
-}
-
-static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
- void(*func)(TCGv, TCGv, TCGv))
-{
- TCGv source1, source2;
- source1 = tcg_temp_new();
- source2 = tcg_temp_new();
-
- gen_get_gpr(ctx, source1, a->rs1);
- gen_get_gpr(ctx, source2, a->rs2);
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_ext32u_tl(source2, source2);
-
- (*func)(source1, source1, source2);
-
- tcg_gen_ext32s_tl(source1, source1);
- gen_set_gpr(ctx, a->rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
- return true;
-}
-
static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_deposit_tl(ret, arg1, arg2,
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc
b/target/riscv/insn_trans/trans_rvm.c.inc
index 013b3f7009..3d93b24c25 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -99,30 +99,30 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
-
- return gen_arith_div_w(ctx, a, &gen_div);
+ ctx->w = true;
+ return gen_arith(ctx, a, EXT_SIGN, gen_div);
}
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
-
- return gen_arith_div_uw(ctx, a, &gen_divu);
+ ctx->w = true;
+ return gen_arith(ctx, a, EXT_ZERO, gen_divu);
}
static bool trans_remw(DisasContext *ctx, arg_remw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
-
- return gen_arith_div_w(ctx, a, &gen_rem);
+ ctx->w = true;
+ return gen_arith(ctx, a, EXT_SIGN, gen_rem);
}
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
-
- return gen_arith_div_uw(ctx, a, &gen_remu);
+ ctx->w = true;
+ return gen_arith(ctx, a, EXT_ZERO, gen_remu);
}
--
2.25.1
- [PATCH v3 00/21] target/riscv: Use tcg_constant_*, Richard Henderson, 2021/08/19
- [PATCH v3 02/21] target/riscv: Clean up division helpers, Richard Henderson, 2021/08/19
- [PATCH v3 01/21] target/riscv: Use tcg_constant_*, Richard Henderson, 2021/08/19
- [PATCH v3 04/21] target/riscv: Introduce DisasExtend and new helpers, Richard Henderson, 2021/08/19
- [PATCH v3 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr, Richard Henderson, 2021/08/19
- [PATCH v3 05/21] target/riscv: Add DisasExtend to gen_arith*, Richard Henderson, 2021/08/19
- [PATCH v3 06/21] target/riscv: Remove gen_arith_div*,
Richard Henderson <=
- [PATCH v3 07/21] target/riscv: Use gen_arith for mulh and mulhu, Richard Henderson, 2021/08/19
- [PATCH v3 08/21] target/riscv: Move gen_* helpers for RVM, Richard Henderson, 2021/08/19
- [PATCH v3 09/21] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/19
- [PATCH v3 10/21] target/riscv: Add DisasExtend to gen_unary, Richard Henderson, 2021/08/19
- [PATCH v3 12/21] target/riscv: Add gen_greviw, Richard Henderson, 2021/08/19
- [PATCH v3 11/21] target/riscv: Use DisasExtend in shift operations, Richard Henderson, 2021/08/19
- [PATCH v3 13/21] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/19
- [PATCH v3 14/21] target/riscv: Use {get, dest}_gpr for integer load/store, Richard Henderson, 2021/08/19
- [PATCH v3 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw, Richard Henderson, 2021/08/19