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Re: [PATCH v4 13/21] target/riscv: Use get_gpr in branches
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v4 13/21] target/riscv: Use get_gpr in branches |
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Date: |
Mon, 23 Aug 2021 16:19:40 +1000 |
On Sat, Aug 21, 2021 at 3:58 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Narrow the scope of t0 in trans_jalr.
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 25 ++++++++++---------------
> 1 file changed, 10 insertions(+), 15 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index e25f64c45a..af3e0bc0e6 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -54,24 +54,25 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
>
> static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
> {
> - /* no chaining with JALR */
> TCGLabel *misaligned = NULL;
> - TCGv t0 = tcg_temp_new();
>
> -
> - gen_get_gpr(ctx, cpu_pc, a->rs1);
> - tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
> + tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
> tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
>
> if (!has_ext(ctx, RVC)) {
> + TCGv t0 = tcg_temp_new();
> +
> misaligned = gen_new_label();
> tcg_gen_andi_tl(t0, cpu_pc, 0x2);
> tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
> + tcg_temp_free(t0);
> }
>
> if (a->rd != 0) {
> tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
> }
> +
> + /* No chaining with JALR. */
> lookup_and_goto_ptr(ctx);
>
> if (misaligned) {
> @@ -80,21 +81,18 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
> }
> ctx->base.is_jmp = DISAS_NORETURN;
>
> - tcg_temp_free(t0);
> return true;
> }
>
> static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
> {
> TCGLabel *l = gen_new_label();
> - TCGv source1, source2;
> - source1 = tcg_temp_new();
> - source2 = tcg_temp_new();
> - gen_get_gpr(ctx, source1, a->rs1);
> - gen_get_gpr(ctx, source2, a->rs2);
> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
> + TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
>
> - tcg_gen_brcond_tl(cond, source1, source2, l);
> + tcg_gen_brcond_tl(cond, src1, src2, l);
> gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
> +
> gen_set_label(l); /* branch taken */
>
> if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
> @@ -105,9 +103,6 @@ static bool gen_branch(DisasContext *ctx, arg_b *a,
> TCGCond cond)
> }
> ctx->base.is_jmp = DISAS_NORETURN;
>
> - tcg_temp_free(source1);
> - tcg_temp_free(source2);
> -
> return true;
> }
>
> --
> 2.25.1
>
>
- [PATCH v4 08/21] target/riscv: Use gen_arith for mulh and mulhu, (continued)
- [PATCH v4 08/21] target/riscv: Use gen_arith for mulh and mulhu, Richard Henderson, 2021/08/20
- [PATCH v4 05/21] target/riscv: Introduce DisasExtend and new helpers, Richard Henderson, 2021/08/20
- [PATCH v4 09/21] target/riscv: Move gen_* helpers for RVM, Richard Henderson, 2021/08/20
- [PATCH v4 11/21] target/riscv: Add DisasExtend to gen_unary, Richard Henderson, 2021/08/20
- [PATCH v4 10/21] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/20
- [PATCH v4 01/21] target/riscv: Use tcg_constant_*, Richard Henderson, 2021/08/20
- [PATCH v4 07/21] target/riscv: Remove gen_arith_div*, Richard Henderson, 2021/08/20
- [PATCH v4 13/21] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/20
- Re: [PATCH v4 13/21] target/riscv: Use get_gpr in branches,
Alistair Francis <=
- [PATCH v4 12/21] target/riscv: Use DisasExtend in shift operations, Richard Henderson, 2021/08/20
- [PATCH v4 16/21] target/riscv: Use {get,dest}_gpr for RVA, Richard Henderson, 2021/08/20
- [PATCH v4 14/21] target/riscv: Use {get, dest}_gpr for integer load/store, Richard Henderson, 2021/08/20
- [PATCH v4 20/21] target/riscv: Tidy trans_rvh.c.inc, Richard Henderson, 2021/08/20
- [PATCH v4 15/21] target/riscv: Reorg csr instructions, Richard Henderson, 2021/08/20
- [PATCH v4 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw, Richard Henderson, 2021/08/20