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Re: [PATCH v4 14/21] target/riscv: Use {get, dest}_gpr for integer load/
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v4 14/21] target/riscv: Use {get, dest}_gpr for integer load/store |
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Date: |
Mon, 23 Aug 2021 17:04:13 +1000 |
On Sat, Aug 21, 2021 at 3:59 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 36 +++++++++++++------------
> 1 file changed, 19 insertions(+), 17 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index af3e0bc0e6..f616a26c82 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -138,15 +138,17 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
>
> static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
> {
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> - gen_get_gpr(ctx, t0, a->rs1);
> - tcg_gen_addi_tl(t0, t0, a->imm);
> + TCGv dest = dest_gpr(ctx, a->rd);
> + TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
>
> - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
> - gen_set_gpr(ctx, a->rd, t1);
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> + if (a->imm) {
> + TCGv temp = temp_new(ctx);
> + tcg_gen_addi_tl(temp, addr, a->imm);
> + addr = temp;
> + }
> +
> + tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
> + gen_set_gpr(ctx, a->rd, dest);
> return true;
> }
>
> @@ -177,19 +179,19 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
>
> static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
> {
> - TCGv t0 = tcg_temp_new();
> - TCGv dat = tcg_temp_new();
> - gen_get_gpr(ctx, t0, a->rs1);
> - tcg_gen_addi_tl(t0, t0, a->imm);
> - gen_get_gpr(ctx, dat, a->rs2);
> + TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
> + TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
>
> - tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
> - tcg_temp_free(t0);
> - tcg_temp_free(dat);
> + if (a->imm) {
> + TCGv temp = temp_new(ctx);
> + tcg_gen_addi_tl(temp, addr, a->imm);
> + addr = temp;
> + }
> +
> + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
> return true;
> }
>
> -
> static bool trans_sb(DisasContext *ctx, arg_sb *a)
> {
> return gen_store(ctx, a, MO_SB);
> --
> 2.25.1
>
>
- [PATCH v4 10/21] target/riscv: Move gen_* helpers for RVB, (continued)
- [PATCH v4 10/21] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/20
- [PATCH v4 01/21] target/riscv: Use tcg_constant_*, Richard Henderson, 2021/08/20
- [PATCH v4 07/21] target/riscv: Remove gen_arith_div*, Richard Henderson, 2021/08/20
- [PATCH v4 13/21] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/20
- [PATCH v4 12/21] target/riscv: Use DisasExtend in shift operations, Richard Henderson, 2021/08/20
- [PATCH v4 16/21] target/riscv: Use {get,dest}_gpr for RVA, Richard Henderson, 2021/08/20
- [PATCH v4 14/21] target/riscv: Use {get, dest}_gpr for integer load/store, Richard Henderson, 2021/08/20
- Re: [PATCH v4 14/21] target/riscv: Use {get, dest}_gpr for integer load/store,
Alistair Francis <=
- [PATCH v4 20/21] target/riscv: Tidy trans_rvh.c.inc, Richard Henderson, 2021/08/20
- [PATCH v4 15/21] target/riscv: Reorg csr instructions, Richard Henderson, 2021/08/20
- [PATCH v4 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw, Richard Henderson, 2021/08/20
- [PATCH v4 18/21] target/riscv: Use {get,dest}_gpr for RVF, Richard Henderson, 2021/08/20
- [PATCH v4 19/21] target/riscv: Use {get,dest}_gpr for RVD, Richard Henderson, 2021/08/20
- [PATCH v4 21/21] target/riscv: Use {get,dest}_gpr for RVV, Richard Henderson, 2021/08/20
- Re: [PATCH v4 00/21] target/riscv: Use tcg_constant_*, Alistair Francis, 2021/08/30