Re: [PATCH v3 01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs pro

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Re: [PATCH v3 01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs pro

From:	Richard Henderson
Subject:	Re: [PATCH v3 01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
Date:	Mon, 23 Aug 2021 09:58:36 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0

On 8/23/21 9:40 AM, Philipp Tomsich wrote:

The bitmanipulation ISA extensions will be ratified as individual
small extension packages instead of a large B-extension.  The first
new instructions through the door (these have completed public review)
are Zb[abcs].

This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
these in target/riscv/cpu.[ch].

Signed-off-by: Philipp Tomsich<philipp.tomsich@vrull.eu>
---

Changes in v3:
- Split off removal of 'x-b' property and 'ext_b' field into a separate
   patch to ensure bisectability.

  target/riscv/cpu.c | 4 ++++
  target/riscv/cpu.h | 4 ++++
  2 files changed, 8 insertions(+)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

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[PATCH v3 00/15] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/08/23
- [PATCH v3 02/15] target/riscv: Reassign instructions to the Zba-extension, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 02/15] target/riscv: Reassign instructions to the Zba-extension, Richard Henderson, 2021/08/23
- [PATCH v3 03/15] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 03/15] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits, Richard Henderson, 2021/08/23
- [PATCH v3 04/15] target/riscv: Remove the W-form instructions from Zbs, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 04/15] target/riscv: Remove the W-form instructions from Zbs, Richard Henderson, 2021/08/23
- [PATCH v3 05/15] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 05/15] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Richard Henderson, 2021/08/23
- [PATCH v3 01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Richard Henderson <=
- [PATCH v3 06/15] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 06/15] target/riscv: Reassign instructions to the Zbs-extension, Richard Henderson, 2021/08/23
- [PATCH v3 10/15] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 10/15] target/riscv: Add a REQUIRE_32BIT macro, Richard Henderson, 2021/08/23
- [PATCH v3 12/15] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 12/15] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Richard Henderson, 2021/08/23
- [PATCH v3 07/15] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 07/15] target/riscv: Add instructions of the Zbc-extension, Richard Henderson, 2021/08/23
- [PATCH v3 08/15] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 08/15] target/riscv: Reassign instructions to the Zbb-extension, Richard Henderson, 2021/08/23

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