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[PATCH v2 8/9] hw/arm: xlnx-zynqmp: Add Xilinx eFUSE device
From: |
Tong Ho |
Subject: |
[PATCH v2 8/9] hw/arm: xlnx-zynqmp: Add Xilinx eFUSE device |
Date: |
Mon, 23 Aug 2021 10:49:23 -0700 |
Connect the support for ZynqMP eFUSE one-time field-programmable
bit array.
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
---
hw/arm/xlnx-zynqmp.c | 29 +++++++++++++++++++++++++++++
include/hw/arm/xlnx-zynqmp.h | 3 +++
2 files changed, 32 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 8e39b7d6c7..9e458ad1c0 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -65,6 +65,9 @@
#define BBRAM_ADDR 0xffcd0000
#define BBRAM_IRQ 11
+#define EFUSE_ADDR 0xffcc0000
+#define EFUSE_IRQ 87
+
#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
@@ -241,6 +244,31 @@ static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s,
qemu_irq *gic)
sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
}
+static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ Object *bits = OBJECT(&s->efuse_bits);
+ Object *ctrl = OBJECT(&s->efuse);
+ SysBusDevice *sbd;
+
+ object_initialize_child(OBJECT(s), "efuse", &s->efuse,
+ TYPE_XLNX_ZYNQMP_EFUSE);
+
+ object_initialize_child_with_props(ctrl, "efuse-bits", bits,
+ sizeof(s->efuse_bits),
+ TYPE_XLNX_EFUSE, &error_abort,
+ "efuse-nr", "3",
+ "efuse-size", "2048",
+ NULL);
+
+ qdev_realize(DEVICE(bits), NULL, &error_abort);
+ object_property_set_link(ctrl, "efuse", bits, &error_abort);
+
+ sbd = SYS_BUS_DEVICE(ctrl);
+ sysbus_realize(sbd, &error_abort);
+ sysbus_mmio_map(sbd, 0, EFUSE_ADDR);
+ sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
+}
+
static void xlnx_zynqmp_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -636,6 +664,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
xlnx_zynqmp_create_bbram(s, gic_spi);
+ xlnx_zynqmp_create_efuse(s, gic_spi);
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 07ebcefbab..876e8bf4e3 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -37,6 +37,7 @@
#include "net/can_emu.h"
#include "hw/dma/xlnx_csu_dma.h"
#include "hw/nvram/xlnx-bbram.h"
+#include "hw/nvram/xlnx-zynqmp-efuse.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -97,6 +98,8 @@ struct XlnxZynqMPState {
MemoryRegion *ddr_ram;
MemoryRegion ddr_ram_low, ddr_ram_high;
XlnxBBRam bbram;
+ XlnxZynqMPEFuse efuse;
+ XLNXEFuse efuse_bits;
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
--
2.25.1
- [PATCH v2 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM, Tong Ho, 2021/08/23
- [PATCH v2 8/9] hw/arm: xlnx-zynqmp: Add Xilinx eFUSE device,
Tong Ho <=
- [PATCH v2 5/9] hw/arm: xlnx-versal: Add Xilinx BBRAM device, Tong Ho, 2021/08/23
- [PATCH v2 4/9] hw/nvram: Introduce Xilinx battery-backed ram, Tong Ho, 2021/08/23
- [PATCH v2 1/9] hw/nvram: Introduce Xilinx eFuse QOM, Tong Ho, 2021/08/23
- [PATCH v2 7/9] hw/arm: xlnx-zynqmp: Add Xilinx BBRAM device, Tong Ho, 2021/08/23
- [PATCH v2 6/9] hw/arm: xlnx-versal: Add Xilinx eFUSE device, Tong Ho, 2021/08/23
- [PATCH v2 2/9] hw/nvram: Introduce Xilinx Versal eFuse device, Tong Ho, 2021/08/23
- [PATCH v2 9/9] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage, Tong Ho, 2021/08/23
- [PATCH v2 3/9] hw/nvram: Introduce Xilinx ZynqMP eFuse device, Tong Ho, 2021/08/23
- Re: [PATCH v2 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM, Edgar E. Iglesias, 2021/08/26