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[PATCH v5 08/24] target/riscv: Use gen_arith for mulh and mulhu
From: |
Richard Henderson |
Subject: |
[PATCH v5 08/24] target/riscv: Use gen_arith for mulh and mulhu |
Date: |
Mon, 23 Aug 2021 12:55:13 -0700 |
Split out gen_mulh and gen_mulhu and use the common helper.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvm.c.inc | 40 +++++++++++--------------
1 file changed, 18 insertions(+), 22 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc
b/target/riscv/insn_trans/trans_rvm.c.inc
index 3d93b24c25..80552be7a3 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -25,20 +25,18 @@ static bool trans_mul(DisasContext *ctx, arg_mul *a)
return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
}
+static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
+{
+ TCGv discard = tcg_temp_new();
+
+ tcg_gen_muls2_tl(discard, ret, s1, s2);
+ tcg_temp_free(discard);
+}
+
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
{
REQUIRE_EXT(ctx, RVM);
- TCGv source1 = tcg_temp_new();
- TCGv source2 = tcg_temp_new();
- gen_get_gpr(ctx, source1, a->rs1);
- gen_get_gpr(ctx, source2, a->rs2);
-
- tcg_gen_muls2_tl(source2, source1, source1, source2);
-
- gen_set_gpr(ctx, a->rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
- return true;
+ return gen_arith(ctx, a, EXT_NONE, gen_mulh);
}
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
@@ -47,20 +45,18 @@ static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
}
+static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
+{
+ TCGv discard = tcg_temp_new();
+
+ tcg_gen_mulu2_tl(discard, ret, s1, s2);
+ tcg_temp_free(discard);
+}
+
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
{
REQUIRE_EXT(ctx, RVM);
- TCGv source1 = tcg_temp_new();
- TCGv source2 = tcg_temp_new();
- gen_get_gpr(ctx, source1, a->rs1);
- gen_get_gpr(ctx, source2, a->rs2);
-
- tcg_gen_mulu2_tl(source2, source1, source1, source2);
-
- gen_set_gpr(ctx, a->rd, source1);
- tcg_temp_free(source1);
- tcg_temp_free(source2);
- return true;
+ return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
}
static bool trans_div(DisasContext *ctx, arg_div *a)
--
2.25.1
- [PATCH v5 00/24] target/riscv: Use tcg_constant_*, Richard Henderson, 2021/08/23
- [PATCH v5 02/24] tests/tcg/riscv64: Add test for division, Richard Henderson, 2021/08/23
- [PATCH v5 03/24] target/riscv: Clean up division helpers, Richard Henderson, 2021/08/23
- [PATCH v5 01/24] target/riscv: Use tcg_constant_*, Richard Henderson, 2021/08/23
- [PATCH v5 05/24] target/riscv: Introduce DisasExtend and new helpers, Richard Henderson, 2021/08/23
- [PATCH v5 04/24] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr, Richard Henderson, 2021/08/23
- [PATCH v5 06/24] target/riscv: Add DisasExtend to gen_arith*, Richard Henderson, 2021/08/23
- [PATCH v5 11/24] target/riscv: Add DisasExtend to gen_unary, Richard Henderson, 2021/08/23
- [PATCH v5 07/24] target/riscv: Remove gen_arith_div*, Richard Henderson, 2021/08/23
- [PATCH v5 08/24] target/riscv: Use gen_arith for mulh and mulhu,
Richard Henderson <=
- [PATCH v5 10/24] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/23
- [PATCH v5 13/24] target/riscv: Use extracts for sraiw and srliw, Richard Henderson, 2021/08/23
- [PATCH v5 09/24] target/riscv: Move gen_* helpers for RVM, Richard Henderson, 2021/08/23
- [PATCH v5 15/24] target/riscv: Use {get, dest}_gpr for integer load/store, Richard Henderson, 2021/08/23
- [PATCH v5 16/24] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation, Richard Henderson, 2021/08/23
- [PATCH v5 14/24] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/23