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Re: [PATCH v6 03/14] target/riscv: slli.uw is only a valid encoding if s
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v6 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits |
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Date: |
Mon, 30 Aug 2021 14:46:54 +1000 |
On Thu, Aug 26, 2021 at 3:09 AM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> For RV64, the shamt field in slli.uw is 6 bits wide. While the encoding
> space currently reserves a wider shamt-field (for use is a future RV128
> ISA), setting the additional bit to 1 will not map to slli.uw for RV64
> and needs to be treated as an illegal instruction.
>
> Note that this encoding being reserved for a future RV128 does not imply
> that no other instructions for RV64-only could be added in this encoding
> space in the future.
>
> As the implementation is separate from the gen_shifti helpers, we keep
> it that way and add the check for the shamt-width here.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Instead of defining a new decoding format, we treat slli.uw as if it
> had a 7bit-wide field for shamt (the 7th bit is reserved for RV128)
> and check for validity of the encoding in C code.
>
> target/riscv/insn_trans/trans_rvb.c.inc | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index 3cdd70a2b9..dcc7b6893d 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -430,6 +430,15 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw
> *a)
> REQUIRE_64BIT(ctx);
> REQUIRE_ZBA(ctx);
>
> + /*
> + * The shamt field is only 6 bits for RV64 (with the 7th bit
> + * remaining reserved for RV128). If the reserved bit is set
> + * on RV64, the encoding is illegal.
> + */
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
> +
> TCGv source1 = tcg_temp_new();
> gen_get_gpr(source1, a->rs1);
>
> --
> 2.25.1
>
>
- [PATCH v6 00/14] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/08/25
- [PATCH v6 01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/08/25
- [PATCH v6 02/14] target/riscv: Reassign instructions to the Zba-extension, Philipp Tomsich, 2021/08/25
- [PATCH v6 04/14] target/riscv: Remove the W-form instructions from Zbs, Philipp Tomsich, 2021/08/25
- [PATCH v6 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Philipp Tomsich, 2021/08/25
- [PATCH v6 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits, Philipp Tomsich, 2021/08/25
- Re: [PATCH v6 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits,
Alistair Francis <=
- [PATCH v6 06/14] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/08/25
- [PATCH v6 07/14] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/08/25
- [PATCH v6 08/14] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/08/25
- [PATCH v6 11/14] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/08/25
- [PATCH v6 10/14] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/08/25