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Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instruc
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From: |
Frédéric Pétrot |
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Subject: |
Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions |
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Date: |
Tue, 31 Aug 2021 18:00:54 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 |
Hello Richard,
Le 31/08/2021 à 04:24, Richard Henderson a écrit :
> On 8/30/21 10:16 AM, Frédéric Pétrot wrote:
>> +#if defined(TARGET_RISCV128)
>> +/*
>> + * Accessing signed 64-bit or 128-bit values should be part of MemOp in
>> + * include/exec/memop.h
>> + * Unfortunately, this requires to change the defines there, as MO_SIGN is
>> 4,
>> + * and values 0 to 3 are usual types sizes.
>> + * Note that an assert is triggered when MemOp is MO_SIGN|MO_TEQ, this value
>> + * being some kind of sentinel.
>
> 20210818191920.390759-24-richard.henderson@linaro.org/">https://lore.kernel.org/qemu-devel/20210818191920.390759-24-richard.henderson@linaro.org/
Thanks for the pointer,
Frédéric
>
>
>
> r~
--
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| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
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- [PATCH 1/8] target/riscv: Settings for 128-bit extension support, Frédéric Pétrot, 2021/08/30
- [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions, Frédéric Pétrot, 2021/08/30
- Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions, Philippe Mathieu-Daudé, 2021/08/30
- Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions, Richard Henderson, 2021/08/30
- Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions,
Frédéric Pétrot <=
- Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions, Richard Henderson, 2021/08/30
- [PATCH 4/8] target/riscv: 128-bit arithmetic and logic instructions, Frédéric Pétrot, 2021/08/30
- Re: [PATCH 4/8] target/riscv: 128-bit arithmetic and logic instructions, Richard Henderson, 2021/08/30
- [PATCH 2/8] target/riscv: 128-bit registers creation and access, Frédéric Pétrot, 2021/08/30
- [PATCH 6/8] target/riscv: Support of compiler's 128-bit integer types, Frédéric Pétrot, 2021/08/30