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[PULL 04/33] target/riscv: Don't wrongly override isa version
From: |
Alistair Francis |
Subject: |
[PULL 04/33] target/riscv: Don't wrongly override isa version |
Date: |
Wed, 1 Sep 2021 12:09:29 +1000 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
For some cpu, the isa version has already been set in cpu init function.
Thus only override the isa version when isa version is not set, or
users set different isa version explicitly by cpu parameters.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210811144612.68674-1-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 991a6bb760..1a2b03d579 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -392,9 +392,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
RISCVCPU *cpu = RISCV_CPU(dev);
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
- int priv_version = PRIV_VERSION_1_11_0;
- int bext_version = BEXT_VERSION_0_93_0;
- int vext_version = VEXT_VERSION_0_07_1;
+ int priv_version = 0;
target_ulong target_misa = env->misa;
Error *local_err = NULL;
@@ -417,9 +415,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
}
- set_priv_version(env, priv_version);
- set_bext_version(env, bext_version);
- set_vext_version(env, vext_version);
+ if (priv_version) {
+ set_priv_version(env, priv_version);
+ } else if (!env->priv_ver) {
+ set_priv_version(env, PRIV_VERSION_1_11_0);
+ }
if (cpu->cfg.mmu) {
set_feature(env, RISCV_FEATURE_MMU);
@@ -497,6 +497,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
target_misa |= RVH;
}
if (cpu->cfg.ext_b) {
+ int bext_version = BEXT_VERSION_0_93_0;
target_misa |= RVB;
if (cpu->cfg.bext_spec) {
@@ -515,6 +516,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
set_bext_version(env, bext_version);
}
if (cpu->cfg.ext_v) {
+ int vext_version = VEXT_VERSION_0_07_1;
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
--
2.31.1
- [PULL 00/33] riscv-to-apply queue, Alistair Francis, 2021/08/31
- [PULL 01/33] hw/char: Add config for shakti uart, Alistair Francis, 2021/08/31
- [PULL 02/33] hw/riscv: virt: Move flash node to root, Alistair Francis, 2021/08/31
- [PULL 03/33] target/riscv: Correct a comment in riscv_csrrw(), Alistair Francis, 2021/08/31
- [PULL 04/33] target/riscv: Don't wrongly override isa version,
Alistair Francis <=
- [PULL 05/33] target/riscv: Add User CSRs read-only check, Alistair Francis, 2021/08/31
- [PULL 07/33] hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp(), Alistair Francis, 2021/08/31
- [PULL 06/33] hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv(), Alistair Francis, 2021/08/31
- [PULL 08/33] hw/core/register: Add more 64-bit utilities, Alistair Francis, 2021/08/31
- [PULL 09/33] hw/registerfields: Use 64-bit bitfield for FIELD_DP64, Alistair Francis, 2021/08/31
- [PULL 10/33] target/riscv: Use tcg_constant_*, Alistair Francis, 2021/08/31
- [PULL 11/33] tests/tcg/riscv64: Add test for division, Alistair Francis, 2021/08/31
- [PULL 12/33] target/riscv: Clean up division helpers, Alistair Francis, 2021/08/31
- [PULL 15/33] target/riscv: Add DisasExtend to gen_arith*, Alistair Francis, 2021/08/31
- [PULL 13/33] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr, Alistair Francis, 2021/08/31