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[PATCH v10 14/16] target/riscv: Add zext.h instructions to Zbb, removing
From: |
Philipp Tomsich |
Subject: |
[PATCH v10 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh |
Date: |
Sat, 4 Sep 2021 22:35:13 +0200 |
The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a
zext.h instruction is provided (built on pack/packh from pre-0.93
draft-B) is available.
This commit adds zext.h and removes the pack* instructions.
Note that the encodings for zext.h are different between RV32 and
RV64, which is handled through REQUIRE_32BIT.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v9)
Changes in v9:
- Rebased to 8880cc4362.
Changes in v4:
- Renamed RV32 variant to zext_h_32.
- Reordered trans_zext_h_{32,64} to be next to each other.
Changes in v3:
- Moved zext.h-addition & pack*-removal to a separate commit.
target/riscv/insn32.decode | 12 ++--
target/riscv/insn_trans/trans_rvb.c.inc | 86 ++++---------------------
2 files changed, 21 insertions(+), 77 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 901a66c0f5..affb99b3e6 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -692,6 +692,9 @@ rori 01100 ............ 101 ..... 0010011 @sh
sext_b 011000 000100 ..... 001 ..... 0010011 @r2
sext_h 011000 000101 ..... 001 ..... 0010011 @r2
xnor 0100000 .......... 100 ..... 0110011 @r
+# The encoding for zext.h differs between RV32 and RV64.
+# zext_h_32 denotes the RV32 variant.
+zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
@@ -704,15 +707,14 @@ rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
rolw 0110000 .......... 001 ..... 0111011 @r
roriw 0110000 .......... 101 ..... 0011011 @sh5
rorw 0110000 .......... 101 ..... 0111011 @r
+# The encoding for zext.h differs between RV32 and RV64.
+# When executing on RV64, the encoding used in RV32 is an illegal
+# instruction, so we use different handler functions to differentiate.
+zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
# *** RV32B Standard Extension ***
-pack 0000100 .......... 100 ..... 0110011 @r
-packu 0100100 .......... 100 ..... 0110011 @r
-packh 0000100 .......... 111 ..... 0110011 @r
# *** RV64B Standard Extension (in addition to RV32B) ***
-packw 0000100 .......... 100 ..... 0111011 @r
-packuw 0100100 .......... 100 ..... 0111011 @r
# *** RV32 Zbc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 6fd1a020b3..badc6882eb 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -88,47 +88,6 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
}
-static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
-{
- tcg_gen_deposit_tl(ret, arg1, arg2,
- TARGET_LONG_BITS / 2,
- TARGET_LONG_BITS / 2);
-}
-
-static bool trans_pack(DisasContext *ctx, arg_pack *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_pack);
-}
-
-static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv t = tcg_temp_new();
- tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
- tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
- tcg_temp_free(t);
-}
-
-static bool trans_packu(DisasContext *ctx, arg_packu *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packu);
-}
-
-static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv t = tcg_temp_new();
- tcg_gen_ext8u_tl(t, arg2);
- tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
- tcg_temp_free(t);
-}
-
-static bool trans_packh(DisasContext *ctx, arg_packh *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packh);
-}
-
static bool trans_min(DisasContext *ctx, arg_min *a)
{
REQUIRE_ZBB(ctx);
@@ -336,6 +295,20 @@ GEN_TRANS_SHADD(1)
GEN_TRANS_SHADD(2)
GEN_TRANS_SHADD(3)
+static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
+}
+
+static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZBB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
+}
+
static void gen_clzw(TCGv ret, TCGv arg1)
{
TCGv t = tcg_temp_new();
@@ -372,37 +345,6 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
}
-static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv t = tcg_temp_new();
- tcg_gen_ext16s_tl(t, arg2);
- tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
- tcg_temp_free(t);
-}
-
-static bool trans_packw(DisasContext *ctx, arg_packw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packw);
-}
-
-static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv t = tcg_temp_new();
- tcg_gen_shri_tl(t, arg1, 16);
- tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
- tcg_gen_ext32s_tl(ret, ret);
- tcg_temp_free(t);
-}
-
-static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packuw);
-}
-
static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
{
TCGv_i32 t1 = tcg_temp_new_i32();
--
2.25.1
- [PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions, (continued)
- [PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions, Philipp Tomsich, 2021/09/04
- [PATCH v10 13/16] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/09/04
- [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw(), Philipp Tomsich, 2021/09/04
- [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs, Philipp Tomsich, 2021/09/04
- [PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Philipp Tomsich, 2021/09/04
- [PATCH v10 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh,
Philipp Tomsich <=