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Re: [PATCH v11 1/7] [RISCV_PM] Add J-extension into RISC-V
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v11 1/7] [RISCV_PM] Add J-extension into RISC-V |
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Date: |
Fri, 10 Sep 2021 15:15:31 +0800 |
On Fri, Sep 10, 2021 at 3:00 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- [PATCH v11 0/7] RISC-V Pointer Masking implementation, Alexey Baturo, 2021/09/09
- [PATCH v11 1/7] [RISCV_PM] Add J-extension into RISC-V, Alexey Baturo, 2021/09/09
- Re: [PATCH v11 1/7] [RISCV_PM] Add J-extension into RISC-V,
Bin Meng <=
- [PATCH v11 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode, Alexey Baturo, 2021/09/09
- [PATCH v11 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2021/09/09
- [PATCH v11 2/7] [RISCV_PM] Add CSR defines for RISC-V PM extension, Alexey Baturo, 2021/09/09
- [PATCH v11 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs, Alexey Baturo, 2021/09/09
- [PATCH v11 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension, Alexey Baturo, 2021/09/09
- [PATCH v11 7/7] [RISCV_PM] Allow experimental J-ext to be turned on, Alexey Baturo, 2021/09/09