Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shif

qemu-devel

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shif

From:	Richard Henderson
Subject:	Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
Date:	Fri, 10 Sep 2021 15:57:47 +0200
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 9/10/21 3:47 PM, Philipp Tomsich wrote:

Just wondering regarding the UXL-comment: the clzw instruction will be an illegal encodingfor RV32 (the w-form instructions are present on RV64 only), so it should never beencountered in a RV32 instruction stream.


Correct.

Did you mean that clz (the instruction operating on xlen-registers) would have 
ctx->w
set for RV32 executing on RV64 ... or am I missing something fundamental?


Yes.

Or, as some test patches I was planning to post this weekend, replacing "w" as booleanwith an "operation length" (ol) as an enum of MXL_RV*, so that we can represent "d"operations on RV128 with the same mechanism.

r~

[Prev in Thread]

Current Thread

[Next in Thread]

Re: [PATCH v10 10/16] target/riscv: Reassign instructions to the Zbb-extension, (continued)
- [PATCH v10 09/16] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/09/04
- [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/09/04
  - Re: [PATCH v10 12/16] target/riscv: Add a REQUIRE_32BIT macro, Bin Meng, 2021/09/08
- [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/04
  - Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson, 2021/09/05
    - Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/05
    - Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/10
    - Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson, 2021/09/10
    - Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Philipp Tomsich, 2021/09/10
    - Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic), Richard Henderson <=
- [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]), Philipp Tomsich, 2021/09/04
  - Re: [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]), Bin Meng, 2021/09/08
- [PATCH v10 16/16] disas/riscv: Add Zb[abcs] instructions, Philipp Tomsich, 2021/09/04
- [PATCH v10 13/16] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/09/04
- [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw(), Philipp Tomsich, 2021/09/04
  - Re: [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw(), Richard Henderson, 2021/09/05
  - Re: [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw(), Alistair Francis, 2021/09/06
  - Re: [PATCH v10 01/16] target/riscv: Introduce temporary in gen_add_uw(), Bin Meng, 2021/09/08
- [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs, Philipp Tomsich, 2021/09/04
  - Re: [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs, Bin Meng, 2021/09/08

Prev by Date: Re: [PATCH 1/5] docs/devel: document expectations for QAPI data modelling for QMP
Next by Date: Re: [PATCH RFC server v2 00/11] vfio-user server in QEMU
Previous by thread: Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
Next by thread: [PATCH v10 15/16] target/riscv: Remove RVB (replaced by Zb[abcs])
Index(es):
- Date
- Thread