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Re: [PATCH 2/4] hw/dma: sifive_pdma: claim bit must be set before DMA tr
From: |
Bin Meng |
Subject: |
Re: [PATCH 2/4] hw/dma: sifive_pdma: claim bit must be set before DMA transactions |
Date: |
Sat, 11 Sep 2021 22:48:11 +0800 |
On Fri, Sep 10, 2021 at 1:58 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Real PDMA must have Control.claim bit to be set before
> Control.run bit is set to start any DMA transactions.
> Otherwise nothing will be transferred.
>
> The following result is PDMA tested in U-boot on Unmatched board:
%s/U-boot/U-Boot
>
> => mw.l 0x3000000 0x0 <= Disclaim channel 0
> (Channel 0 is not claimed)
> => mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32
> bytes)
> => mw.q 0x3000008 0x2 <= NextBytes = 2
> => mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000
> => mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000
> => mw.l 0x84000000 0x87654321 <= Fill test data to dst
> => mw.l 0x84001000 0x12345678 <= Fill test data to src
> => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
> 84000000: 87654321 !Ce.
> 84001000: 12345678 xV4.
> => md.l 0x3000000 8 <= Dump PDMA status
> 03000000: 00000000 55000000 00000002 00000000 .......U........
> 03000010: 84000000 00000000 84001000 00000000 ................
> => mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits
> => md.l 0x3000000 8 <= Dump PDMA status
> 03000000: 00000001 66000000 00000000 00000000 .......f........
> 03000010: 00000000 00000000 00000000 00000000 ................
> => md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
> 84000000: 87654321 !Ce.
> 84001000: 12345678 xV4.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Tested-by: Max Hsu <max.hsu@sifive.com>
> ---
> hw/dma/sifive_pdma.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>