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Re: [PATCH v2 17/22] target/riscv: Allow users to force enable AIA CSRs
From: |
Alistair Francis |
Subject: |
Re: [PATCH v2 17/22] target/riscv: Allow users to force enable AIA CSRs in HART |
Date: |
Wed, 15 Sep 2021 11:16:18 +1000 |
On Thu, Sep 2, 2021 at 10:03 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> We add "x-aia" command-line option for RISC-V HART using which
> allows users to force enable CPU AIA CSRs without changing the
> interrupt controller available in RISC-V machine.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 5 +++++
> target/riscv/cpu.h | 1 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e0f4ae4224..9723d54eaf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -452,6 +452,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> }
> }
>
> + if (cpu->cfg.aia) {
> + riscv_set_feature(env, RISCV_FEATURE_AIA);
> + }
> +
> set_resetvec(env, cpu->cfg.resetvec);
>
> /* If only XLEN is set for misa, then set misa from properties */
> @@ -672,6 +676,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> + DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
>
> DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
> DEFINE_PROP_END_OF_LIST(),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 16a4596433..cab9e90153 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -337,6 +337,7 @@ struct RISCVCPU {
> bool mmu;
> bool pmp;
> bool epmp;
> + bool aia;
> uint64_t resetvec;
> } cfg;
> };
> --
> 2.25.1
>
>
- [PATCH v2 07/22] target/riscv: Add defines for AIA CSRs, (continued)
- [PATCH v2 07/22] target/riscv: Add defines for AIA CSRs, Anup Patel, 2021/09/02
- [PATCH v2 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2021/09/02
- [PATCH v2 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2021/09/02
- [PATCH v2 12/22] target/riscv: Implement AIA interrupt filtering CSRs, Anup Patel, 2021/09/02
- [PATCH v2 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2021/09/02
- [PATCH v2 14/22] target/riscv: Implement AIA xiselect and xireg CSRs, Anup Patel, 2021/09/02
- [PATCH v2 15/22] target/riscv: Implement AIA IMSIC interface CSRs, Anup Patel, 2021/09/02
- [PATCH v2 16/22] hw/riscv: virt: Use AIA INTC compatible string when available, Anup Patel, 2021/09/02
- [PATCH v2 17/22] target/riscv: Allow users to force enable AIA CSRs in HART, Anup Patel, 2021/09/02
- Re: [PATCH v2 17/22] target/riscv: Allow users to force enable AIA CSRs in HART,
Alistair Francis <=
- [PATCH v2 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine, Anup Patel, 2021/09/02
- [PATCH v2 18/22] hw/intc: Add RISC-V AIA APLIC device emulation, Anup Patel, 2021/09/02
- [PATCH v2 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation, Anup Patel, 2021/09/02
- [PATCH v2 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Anup Patel, 2021/09/02
- [PATCH v2 22/22] docs/system: riscv: Document AIA options for virt machine, Anup Patel, 2021/09/02
- Re: [PATCH v2 00/22] QEMU RISC-V AIA support, Bin Meng, 2021/09/04