[RFC 09/10] target/riscv: rvb: fixed an issue about clzw instruction

[Eric Tang]

Signed-off-by: Eric Tang <tangxingxin1008@gmail.com>

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index 39ca5a573f..4523a5cd4c 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -456,7 +456,7 @@ GEN_TRANS_SHADD(3)
 
 static void gen_clzw(TCGv ret, TCGv arg1)
 {
-    tcg_gen_clzi_tl(ret, ret, 64);
+    tcg_gen_clzi_tl(ret, arg1, 64);
     tcg_gen_subi_tl(ret, ret, 32);
 }
 
@@ -464,6 +464,7 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
+    ctx->w = true;
     return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
 }
 
-- 
2.17.1