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[PATCH 11/30] tcg/loongarch: Implement sign-/zero-extension ops
From: |
WANG Xuerui |
Subject: |
[PATCH 11/30] tcg/loongarch: Implement sign-/zero-extension ops |
Date: |
Mon, 20 Sep 2021 16:04:32 +0800 |
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
tcg/loongarch/tcg-target-con-set.h | 1 +
tcg/loongarch/tcg-target.c.inc | 82 ++++++++++++++++++++++++++++++
2 files changed, 83 insertions(+)
diff --git a/tcg/loongarch/tcg-target-con-set.h
b/tcg/loongarch/tcg-target-con-set.h
index 5cc4407367..7e459490ea 100644
--- a/tcg/loongarch/tcg-target-con-set.h
+++ b/tcg/loongarch/tcg-target-con-set.h
@@ -15,3 +15,4 @@
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
C_O0_I1(r)
+C_O1_I1(r, r)
diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc
index 9d78146fb9..0ee389fdaa 100644
--- a/tcg/loongarch/tcg-target.c.inc
+++ b/tcg/loongarch/tcg-target.c.inc
@@ -332,6 +332,36 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg rd,
tcg_out_opc_cu52i_d(s, rd, rd, top);
}
+static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_andi(s, ret, arg, 0xff);
+}
+
+static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15);
+}
+
+static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31);
+}
+
+static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_sext_b(s, ret, arg);
+}
+
+static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_sext_h(s, ret, arg);
+}
+
+static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_addi_w(s, ret, arg, 0);
+}
+
/*
* Entry-points
*/
@@ -341,6 +371,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const int const_args[TCG_MAX_OP_ARGS])
{
TCGArg a0 = args[0];
+ TCGArg a1 = args[1];
switch (opc) {
case INDEX_op_mb:
@@ -351,6 +382,41 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0);
break;
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
+ tcg_out_ext8s(s, a0, a1);
+ break;
+
+ case INDEX_op_ext8u_i32:
+ case INDEX_op_ext8u_i64:
+ tcg_out_ext8u(s, a0, a1);
+ break;
+
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
+ tcg_out_ext16s(s, a0, a1);
+ break;
+
+ case INDEX_op_ext16u_i32:
+ case INDEX_op_ext16u_i64:
+ tcg_out_ext16u(s, a0, a1);
+ break;
+
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_extu_i32_i64:
+ tcg_out_ext32u(s, a0, a1);
+ break;
+
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_extrl_i64_i32:
+ case INDEX_op_ext_i32_i64:
+ tcg_out_ext32s(s, a0, a1);
+ break;
+
+ case INDEX_op_extrh_i64_i32:
+ tcg_out_opc_srai_d(s, a0, a1, 32);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@@ -364,6 +430,22 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_goto_ptr:
return C_O0_I1(r);
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext8u_i32:
+ case INDEX_op_ext8u_i64:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext16u_i32:
+ case INDEX_op_ext16u_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
+ case INDEX_op_extrh_i64_i32:
+ case INDEX_op_ext_i32_i64:
+ return C_O1_I1(r, r);
+
default:
g_assert_not_reached();
}
--
2.33.0
- Re: [PATCH 12/30] tcg/loongarch: Implement not/and/or/xor/nor/andc/orc ops, (continued)
- [PATCH 14/30] tcg/loongarch: Implement bswap32_i32/bswap64_i64, WANG Xuerui, 2021/09/20
- [PATCH 04/30] tcg/loongarch: Add generated instruction opcodes and encoding helpers, WANG Xuerui, 2021/09/20
- [PATCH 19/30] tcg/loongarch: Implement br/brcond ops, WANG Xuerui, 2021/09/20
- [PATCH 17/30] tcg/loongarch: Implement neg/add/sub ops, WANG Xuerui, 2021/09/20
- [PATCH 11/30] tcg/loongarch: Implement sign-/zero-extension ops,
WANG Xuerui <=
- [PATCH 20/30] tcg/loongarch: Implement setcond ops, WANG Xuerui, 2021/09/20
- [PATCH 15/30] tcg/loongarch: Implement clz/ctz ops, WANG Xuerui, 2021/09/20
- [PATCH 18/30] tcg/loongarch: Implement mul/mulsh/muluh/div/divu/rem/remu ops, WANG Xuerui, 2021/09/20
- [PATCH 08/30] tcg/loongarch: Implement the memory barrier op, WANG Xuerui, 2021/09/20
- [PATCH 24/30] tcg/loongarch: Implement tcg_target_qemu_prologue, WANG Xuerui, 2021/09/20