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[PULL v2 07/21] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU
From: |
Alistair Francis |
Subject: |
[PULL v2 07/21] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines |
Date: |
Tue, 21 Sep 2021 16:53:58 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
---
include/hw/timer/ibex_timer.h | 2 ++
hw/riscv/opentitan.c | 3 +++
hw/timer/ibex_timer.c | 17 ++++++++++++-----
3 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h
index 6a43537003..b6f69b38ee 100644
--- a/include/hw/timer/ibex_timer.h
+++ b/include/hw/timer/ibex_timer.h
@@ -48,5 +48,7 @@ struct IbexTimerState {
uint32_t timebase_freq;
qemu_irq irq;
+
+ qemu_irq m_timer_irq;
};
#endif /* HW_IBEX_TIMER_H */
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 048aced0ec..f7cfcf1c3a 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -183,6 +183,9 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc,
Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
0, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_TIMER_TIMEREXPIRED0_0));
+ qdev_connect_gpio_out(DEVICE(&s->timer), 0,
+ qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
+ IRQ_M_TIMER));
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c
index 5befb53506..66e1f8e48c 100644
--- a/hw/timer/ibex_timer.c
+++ b/hw/timer/ibex_timer.c
@@ -77,7 +77,7 @@ static void ibex_timer_update_irqs(IbexTimerState *s)
/*
* If the mtimecmp was in the past raise the interrupt now.
*/
- riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
+ qemu_irq_raise(s->m_timer_irq);
if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
qemu_set_irq(s->irq, true);
@@ -86,7 +86,7 @@ static void ibex_timer_update_irqs(IbexTimerState *s)
}
/* Setup a timer to trigger the interrupt in the future */
- riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
+ qemu_irq_lower(s->m_timer_irq);
qemu_set_irq(s->irq, false);
diff = cpu->env.timecmp - now;
@@ -106,10 +106,8 @@ static void ibex_timer_update_irqs(IbexTimerState *s)
static void ibex_timer_cb(void *opaque)
{
IbexTimerState *s = opaque;
- CPUState *cs = qemu_get_cpu(0);
- RISCVCPU *cpu = RISCV_CPU(cs);
- riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
+ qemu_irq_raise(s->m_timer_irq);
if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
qemu_set_irq(s->irq, true);
@@ -280,12 +278,21 @@ static void ibex_timer_init(Object *obj)
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
}
+static void ibex_timer_realize(DeviceState *dev, Error **errp)
+{
+ IbexTimerState *s = IBEX_TIMER(dev);
+
+ qdev_init_gpio_out(dev, &s->m_timer_irq, 1);
+}
+
+
static void ibex_timer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = ibex_timer_reset;
dc->vmsd = &vmstate_ibex_timer;
+ dc->realize = ibex_timer_realize;
device_class_set_props(dc, ibex_timer_properties);
}
--
2.31.1
- [PULL v2 00/21] riscv-to-apply queue, Alistair Francis, 2021/09/21
- [PULL v2 02/21] target/riscv: Fix satp write, Alistair Francis, 2021/09/21
- [PULL v2 01/21] target/riscv: Update the ePMP CSR address, Alistair Francis, 2021/09/21
- [PULL v2 03/21] target/riscv: Expose interrupt pending bits as GPIO lines, Alistair Francis, 2021/09/21
- [PULL v2 04/21] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines, Alistair Francis, 2021/09/21
- [PULL v2 05/21] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines, Alistair Francis, 2021/09/21
- [PULL v2 06/21] hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines, Alistair Francis, 2021/09/21
- [PULL v2 07/21] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines,
Alistair Francis <=
- [PULL v2 08/21] hw/timer: Add SiFive PWM support, Alistair Francis, 2021/09/21
- [PULL v2 09/21] sifive_u: Connect the SiFive PWM device, Alistair Francis, 2021/09/21
- [PULL v2 10/21] hw/intc: Rename sifive_clint sources to riscv_aclint sources, Alistair Francis, 2021/09/21
- [PULL v2 11/21] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT, Alistair Francis, 2021/09/21
- [PULL v2 12/21] hw/riscv: virt: Re-factor FDT generation, Alistair Francis, 2021/09/21
- [PULL v2 13/21] hw/riscv: virt: Add optional ACLINT support to virt machine, Alistair Francis, 2021/09/21
- [PULL v2 14/21] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set, Alistair Francis, 2021/09/21
- [PULL v2 15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions, Alistair Francis, 2021/09/21
- [PULL v2 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions, Alistair Francis, 2021/09/21
- [PULL v2 17/21] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer, Alistair Francis, 2021/09/21