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[PULL v2 19/21] target/riscv: Backup/restore mstatus.SD bit when virtual
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From: |
Alistair Francis |
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Subject: |
[PULL v2 19/21] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped |
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Date: |
Tue, 21 Sep 2021 16:54:10 +1000 |
From: Frank Chang <frank.chang@sifive.com>
When virtual registers are swapped, mstatus.SD bit should also be
backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept
across the world switches.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210914013717.881430-1-frank.chang@sifive.com
[ Changes by AF:
- Convert variable to a uint64_t to fix clang error
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 701858d670..d41d5cd27c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -106,9 +106,10 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
{
+ uint64_t sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
- MSTATUS64_UXL;
+ MSTATUS64_UXL | sd;
bool current_virt = riscv_cpu_virt_enabled(env);
g_assert(riscv_has_ext(env, RVH));
--
2.31.1
- [PULL v2 09/21] sifive_u: Connect the SiFive PWM device, (continued)
- [PULL v2 09/21] sifive_u: Connect the SiFive PWM device, Alistair Francis, 2021/09/21
- [PULL v2 10/21] hw/intc: Rename sifive_clint sources to riscv_aclint sources, Alistair Francis, 2021/09/21
- [PULL v2 11/21] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT, Alistair Francis, 2021/09/21
- [PULL v2 12/21] hw/riscv: virt: Re-factor FDT generation, Alistair Francis, 2021/09/21
- [PULL v2 13/21] hw/riscv: virt: Add optional ACLINT support to virt machine, Alistair Francis, 2021/09/21
- [PULL v2 14/21] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set, Alistair Francis, 2021/09/21
- [PULL v2 15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions, Alistair Francis, 2021/09/21
- [PULL v2 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions, Alistair Francis, 2021/09/21
- [PULL v2 17/21] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer, Alistair Francis, 2021/09/21
- [PULL v2 18/21] docs/system/riscv: sifive_u: Update U-Boot instructions, Alistair Francis, 2021/09/21
- [PULL v2 19/21] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped,
Alistair Francis <=
- [PULL v2 20/21] target/riscv: csr: Rename HCOUNTEREN_CY and friends, Alistair Francis, 2021/09/21
- [PULL v2 21/21] hw/riscv: opentitan: Correct the USB Dev address, Alistair Francis, 2021/09/21
- Re: [PULL v2 00/21] riscv-to-apply queue, Richard Henderson, 2021/09/21