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Re: [RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPID


From: Philippe Mathieu-Daudé
Subject: Re: [RESEND PATCH 1/3] hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset
Date: Tue, 21 Sep 2021 10:13:36 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.1.0

On 9/21/21 05:25, David Gibson wrote:
On Sat, Sep 18, 2021 at 11:26:51AM +0800, Bin Meng wrote:
The reset value of IPIDR should be zero for Freescale chipset, per
the following 2 manuals I checked:

- P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
- P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)

Currently it is set to 1, which leaves the IPI enabled on core 0
after power-on reset. Such may cause unexpected interrupt to be
delivered to core 0 if the IPI is triggered from core 0 to other
cores later.

Fixes: ffd5e9fe0276 ("openpic: Reset IRQ source private members")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/584
Signed-off-by: Bin Meng <bin.meng@windriver.com>

Since these patches are very simple and look sensible, I've applied
them to ppc-for-6.2.

However, you should note that Greg and I are both moving into other
areas and don't have much capacity for ppc maintainership any more.
Therefore I'll shortly be sending some MAINTAINERS updates moving
openpic (amongst other things) to "Orphan" status.

I'm not trying to force Bin to become (yet) another maintainer,
but from his previous contributions, he demonstrated a very good
knowledge of embedded PowerPC ISA & chipsets, his patches have good
quality and description, and he is consistent over time in his
contributions. So if he is interested, I'd vouch for him as a
maintainer for embedded ppc. Now up to him, his time and/or employer :)

Regards,

Phil.



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