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[PATCH v2 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc/
From: |
WANG Xuerui |
Subject: |
[PATCH v2 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc/eqv ops |
Date: |
Wed, 22 Sep 2021 04:18:57 +0800 |
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
tcg/loongarch64/tcg-target-con-set.h | 2 +
tcg/loongarch64/tcg-target.c.inc | 101 +++++++++++++++++++++++++++
2 files changed, 103 insertions(+)
diff --git a/tcg/loongarch64/tcg-target-con-set.h
b/tcg/loongarch64/tcg-target-con-set.h
index 7e459490ea..9ac24b8ad0 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -16,3 +16,5 @@
*/
C_O0_I1(r)
C_O1_I1(r, r)
+C_O1_I2(r, r, rC)
+C_O1_I2(r, r, rU)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index e000a31a06..89fdb6d7c3 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -374,6 +374,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
{
TCGArg a0 = args[0];
TCGArg a1 = args[1];
+ TCGArg a2 = args[2];
+ int c2 = const_args[2];
switch (opc) {
case INDEX_op_mb:
@@ -419,6 +421,79 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_srai_d(s, a0, a1, 32);
break;
+ case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
+ tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO);
+ break;
+
+ case INDEX_op_nor_i32:
+ case INDEX_op_nor_i64:
+ if (c2) {
+ tcg_out_opc_ori(s, a0, a1, a2);
+ tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO);
+ } else {
+ tcg_out_opc_nor(s, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_andc_i32:
+ case INDEX_op_andc_i64:
+ if (c2) {
+ /* guaranteed to fit due to constraint */
+ tcg_out_opc_andi(s, a0, a1, ~a2);
+ } else {
+ tcg_out_opc_andn(s, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_orc_i32:
+ case INDEX_op_orc_i64:
+ if (c2) {
+ /* guaranteed to fit due to constraint */
+ tcg_out_opc_ori(s, a0, a1, ~a2);
+ } else {
+ tcg_out_opc_orn(s, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_eqv_i32:
+ case INDEX_op_eqv_i64:
+ if (c2) {
+ /* guaranteed to fit due to constraint */
+ tcg_out_opc_xori(s, a0, a1, ~a2);
+ } else {
+ tcg_out_opc_nor(s, a0, a2, TCG_REG_ZERO);
+ tcg_out_opc_xor(s, a0, a1, a0);
+ }
+ break;
+
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ if (c2) {
+ tcg_out_opc_andi(s, a0, a1, a2);
+ } else {
+ tcg_out_opc_and(s, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
+ if (c2) {
+ tcg_out_opc_ori(s, a0, a1, a2);
+ } else {
+ tcg_out_opc_or(s, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
+ if (c2) {
+ tcg_out_opc_xori(s, a0, a1, a2);
+ } else {
+ tcg_out_opc_xor(s, a0, a1, a2);
+ }
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@@ -446,8 +521,34 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_ext_i32_i64:
+ case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
return C_O1_I1(r, r);
+ case INDEX_op_andc_i32:
+ case INDEX_op_andc_i64:
+ case INDEX_op_eqv_i32:
+ case INDEX_op_eqv_i64:
+ case INDEX_op_orc_i32:
+ case INDEX_op_orc_i64:
+ /*
+ * LoongArch insns for these ops don't have reg-imm forms, but we
+ * can express using andi/ori/xori if ~constant satisfies
+ * TCG_CT_CONST_U12.
+ */
+ return C_O1_I2(r, r, rC);
+
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ case INDEX_op_nor_i32:
+ case INDEX_op_nor_i64:
+ case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
+ /* LoongArch reg-imm bitops have their imms ZERO-extended */
+ return C_O1_I2(r, r, rU);
+
default:
g_assert_not_reached();
}
--
2.33.0
- [PATCH v2 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi, (continued)
[PATCH v2 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers, WANG Xuerui, 2021/09/21
[PATCH v2 08/30] tcg/loongarch64: Implement the memory barrier op, WANG Xuerui, 2021/09/21
[PATCH v2 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets, WANG Xuerui, 2021/09/21
[PATCH v2 10/30] tcg/loongarch64: Implement goto_ptr, WANG Xuerui, 2021/09/21
[PATCH v2 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc/eqv ops,
WANG Xuerui <=
[PATCH v2 11/30] tcg/loongarch64: Implement sign-/zero-extension ops, WANG Xuerui, 2021/09/21
[PATCH v2 13/30] tcg/loongarch64: Implement deposit/extract ops, WANG Xuerui, 2021/09/21
[PATCH v2 15/30] tcg/loongarch64: Implement clz/ctz ops, WANG Xuerui, 2021/09/21
[PATCH v2 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops, WANG Xuerui, 2021/09/21
[PATCH v2 14/30] tcg/loongarch64: Implement bswap32_i32/bswap32_i64/bswap64_i64, WANG Xuerui, 2021/09/21