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[PATCH v3 19/30] tcg/loongarch64: Implement br/brcond ops
From: |
WANG Xuerui |
Subject: |
[PATCH v3 19/30] tcg/loongarch64: Implement br/brcond ops |
Date: |
Thu, 23 Sep 2021 02:09:16 +0800 |
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 53 ++++++++++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/tcg/loongarch64/tcg-target-con-set.h
b/tcg/loongarch64/tcg-target-con-set.h
index fb56f3a295..367689c2e2 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -15,6 +15,7 @@
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
C_O0_I1(r)
+C_O0_I2(rZ, rZ)
C_O1_I1(r, r)
C_O1_I2(r, r, rC)
C_O1_I2(r, r, ri)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 11fd31ff9d..b65852ef2f 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -386,6 +386,44 @@ static void tcg_out_clzctz(TCGContext *s, LoongArchInsn
opc,
tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0);
}
+/*
+ * Branch helpers
+ */
+
+static const struct {
+ LoongArchInsn op;
+ bool swap;
+} tcg_brcond_to_loongarch[] = {
+ [TCG_COND_EQ] = { OPC_BEQ, false },
+ [TCG_COND_NE] = { OPC_BNE, false },
+ [TCG_COND_LT] = { OPC_BGT, true },
+ [TCG_COND_GE] = { OPC_BLE, true },
+ [TCG_COND_LE] = { OPC_BLE, false },
+ [TCG_COND_GT] = { OPC_BGT, false },
+ [TCG_COND_LTU] = { OPC_BGTU, true },
+ [TCG_COND_GEU] = { OPC_BLEU, true },
+ [TCG_COND_LEU] = { OPC_BLEU, false },
+ [TCG_COND_GTU] = { OPC_BGTU, false }
+};
+
+static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
+ TCGReg arg2, TCGLabel *l)
+{
+ LoongArchInsn op = tcg_brcond_to_loongarch[cond].op;
+
+ tcg_debug_assert(op != 0);
+
+ if (tcg_brcond_to_loongarch[cond].swap) {
+ TCGReg t = arg1;
+ arg1 = arg2;
+ arg2 = t;
+ }
+
+ /* all conditional branch insns belong to DJSk16-format */
+ tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0);
+ tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0));
+}
+
/*
* Entry-points
*/
@@ -408,6 +446,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0);
break;
+ case INDEX_op_br:
+ tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0),
+ 0);
+ tcg_out_opc_b(s, 0);
+ break;
+
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
+ break;
+
case INDEX_op_ext8s_i32:
case INDEX_op_ext8s_i64:
tcg_out_ext8s(s, a0, a1);
@@ -731,6 +780,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_goto_ptr:
return C_O0_I1(r);
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ return C_O0_I2(rZ, rZ);
+
case INDEX_op_ext8s_i32:
case INDEX_op_ext8s_i64:
case INDEX_op_ext8u_i32:
--
2.33.0
- Re: [PATCH v3 01/30] elf: Add machine type value for LoongArch, (continued)
- [PATCH v3 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers, WANG Xuerui, 2021/09/22
- [PATCH v3 08/30] tcg/loongarch64: Implement the memory barrier op, WANG Xuerui, 2021/09/22
- [PATCH v3 06/30] tcg/loongarch64: Define the operand constraints, WANG Xuerui, 2021/09/22
- [PATCH v3 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi, WANG Xuerui, 2021/09/22
- [PATCH v3 07/30] tcg/loongarch64: Implement necessary relocation operations, WANG Xuerui, 2021/09/22
- [PATCH v3 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets, WANG Xuerui, 2021/09/22
- [PATCH v3 10/30] tcg/loongarch64: Implement goto_ptr, WANG Xuerui, 2021/09/22
- [PATCH v3 13/30] tcg/loongarch64: Implement deposit/extract ops, WANG Xuerui, 2021/09/22
- [PATCH v3 17/30] tcg/loongarch64: Implement add/sub ops, WANG Xuerui, 2021/09/22
- [PATCH v3 19/30] tcg/loongarch64: Implement br/brcond ops,
WANG Xuerui <=
- [PATCH v3 11/30] tcg/loongarch64: Implement sign-/zero-extension ops, WANG Xuerui, 2021/09/22
- [PATCH v3 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops, WANG Xuerui, 2021/09/22
- [PATCH v3 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops, WANG Xuerui, 2021/09/22
- [PATCH v3 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops, WANG Xuerui, 2021/09/22
- [PATCH v3 15/30] tcg/loongarch64: Implement clz/ctz ops, WANG Xuerui, 2021/09/22
- [PATCH v3 22/30] tcg/loongarch64: Implement simple load/store ops, WANG Xuerui, 2021/09/22
- [PATCH v3 25/30] tcg/loongarch64: Implement exit_tb/goto_tb, WANG Xuerui, 2021/09/22
- [PATCH v3 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler for loongarch64 hosts, WANG Xuerui, 2021/09/22
- [PATCH v3 27/30] tcg/loongarch64: Register the JIT, WANG Xuerui, 2021/09/22