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[PATCH v4 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops
From: |
WANG Xuerui |
Subject: |
[PATCH v4 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops |
Date: |
Fri, 24 Sep 2021 00:59:23 +0800 |
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++++
tcg/loongarch64/tcg-target.h | 10 +++++-----
2 files changed, 37 insertions(+), 5 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 46b4f54562..ce6843b408 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -519,6 +519,33 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1);
break;
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ tcg_out_opc_revb_2h(s, a0, a1);
+ if (a2 & TCG_BSWAP_OS) {
+ tcg_out_ext16s(s, a0, a0);
+ } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
+ tcg_out_ext16u(s, a0, a0);
+ }
+ break;
+
+ case INDEX_op_bswap32_i32:
+ /* All 32-bit values are computed sign-extended in the register. */
+ a2 = TCG_BSWAP_OS;
+ /* fallthrough */
+ case INDEX_op_bswap32_i64:
+ tcg_out_opc_revb_2w(s, a0, a1);
+ if (a2 & TCG_BSWAP_OS) {
+ tcg_out_ext32s(s, a0, a0);
+ } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
+ tcg_out_ext32u(s, a0, a0);
+ }
+ break;
+
+ case INDEX_op_bswap64_i64:
+ tcg_out_opc_revb_d(s, a0, a1);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@@ -550,6 +577,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_not_i64:
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
return C_O1_I1(r, r);
case INDEX_op_andc_i32:
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 084d635a8e..02d17d2f6d 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -111,8 +111,8 @@ typedef enum {
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
#define TCG_TARGET_HAS_ext16u_i32 1
-#define TCG_TARGET_HAS_bswap16_i32 0
-#define TCG_TARGET_HAS_bswap32_i32 0
+#define TCG_TARGET_HAS_bswap16_i32 1
+#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_neg_i32 0
#define TCG_TARGET_HAS_andc_i32 1
@@ -146,9 +146,9 @@ typedef enum {
#define TCG_TARGET_HAS_ext8u_i64 1
#define TCG_TARGET_HAS_ext16u_i64 1
#define TCG_TARGET_HAS_ext32u_i64 1
-#define TCG_TARGET_HAS_bswap16_i64 0
-#define TCG_TARGET_HAS_bswap32_i64 0
-#define TCG_TARGET_HAS_bswap64_i64 0
+#define TCG_TARGET_HAS_bswap16_i64 1
+#define TCG_TARGET_HAS_bswap32_i64 1
+#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_neg_i64 0
#define TCG_TARGET_HAS_andc_i64 1
--
2.33.0
- [PATCH v4 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets, (continued)
- [PATCH v4 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets, WANG Xuerui, 2021/09/23
- [PATCH v4 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers, WANG Xuerui, 2021/09/23
- [PATCH v4 06/30] tcg/loongarch64: Define the operand constraints, WANG Xuerui, 2021/09/23
- [PATCH v4 08/30] tcg/loongarch64: Implement the memory barrier op, WANG Xuerui, 2021/09/23
- [PATCH v4 07/30] tcg/loongarch64: Implement necessary relocation operations, WANG Xuerui, 2021/09/23
- [PATCH v4 11/30] tcg/loongarch64: Implement sign-/zero-extension ops, WANG Xuerui, 2021/09/23
- [PATCH v4 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi, WANG Xuerui, 2021/09/23
- [PATCH v4 10/30] tcg/loongarch64: Implement goto_ptr, WANG Xuerui, 2021/09/23
- [PATCH v4 15/30] tcg/loongarch64: Implement clz/ctz ops, WANG Xuerui, 2021/09/23
- [PATCH v4 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops,
WANG Xuerui <=
- [PATCH v4 13/30] tcg/loongarch64: Implement deposit/extract ops, WANG Xuerui, 2021/09/23
- [PATCH v4 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops, WANG Xuerui, 2021/09/23
- [PATCH v4 17/30] tcg/loongarch64: Implement add/sub ops, WANG Xuerui, 2021/09/23
- [PATCH v4 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops, WANG Xuerui, 2021/09/23
- [PATCH v4 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops, WANG Xuerui, 2021/09/23
- [PATCH v4 22/30] tcg/loongarch64: Implement simple load/store ops, WANG Xuerui, 2021/09/23
- [PATCH v4 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops, WANG Xuerui, 2021/09/23
- [PATCH v4 27/30] tcg/loongarch64: Register the JIT, WANG Xuerui, 2021/09/23