[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2 2/3] target/riscv: Implement the stval/mtval illegal instr
|
From: |
Alistair Francis |
|
Subject: |
Re: [PATCH v2 2/3] target/riscv: Implement the stval/mtval illegal instruction |
|
Date: |
Wed, 29 Sep 2021 13:56:41 +1000 |
On Fri, Sep 24, 2021 at 10:57 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 9/24/21 2:48 AM, Alistair Francis wrote:
> >> But... more specific to this case. Prior to this, was the exception
> >> handler allowed to
> >> assume anything about the contents of stval? Should the value have been
> >> zero? Would it
> >> be wrong to write to stval unconditionally? How does the guest OS know
> >> that it can rely
> >> on stval being set?
> >
> > As we didn't support writing the illegal instruction stval should be
> > zero before this patch.
>
> Ok, that didn't quite answer the question...
>
> If *wasn't* zero before this patch: we didn't write anything at all, and so
> keep whatever
> previous value the previous exception wrote.
>
> Is that a bug that needs fixing? Because you're still not writing anything
> to stval if
> !MTVAL_INST...
Yeah, that sounds like a bug then.
>
> >> I simply wonder whether it's worthwhile to add the feature and feature
> >> test.
> >
> > Do you just mean have it enabled all the time?
>
> Yes, if without this feature the value of stval was undefined.
Ok, I'll have another look at this. Thanks for pointing this out.
Alistair
>
>
> r~
[PATCH v2 3/3] target/riscv: Set mtval and stval support, Alistair Francis, 2021/09/08