[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 18/23] target/riscv: Remove exit_tb and lookup_and_goto_ptr
From: |
Richard Henderson |
Subject: |
[PATCH v2 18/23] target/riscv: Remove exit_tb and lookup_and_goto_ptr |
Date: |
Tue, 12 Oct 2021 09:21:54 -0700 |
GDB single-stepping is now handled generically, which means
we don't need to do anything in the wrappers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 27 +------------------
.../riscv/insn_trans/trans_privileged.c.inc | 4 +--
target/riscv/insn_trans/trans_rvi.c.inc | 8 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
4 files changed, 7 insertions(+), 34 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d2442f0cf5..6d7fbca1fa 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -149,31 +149,6 @@ static void generate_exception_mtval(DisasContext *ctx,
int excp)
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_exception_debug(void)
-{
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
-}
-
-/* Wrapper around tcg_gen_exit_tb that handles single stepping */
-static void exit_tb(DisasContext *ctx)
-{
- if (ctx->base.singlestep_enabled) {
- gen_exception_debug();
- } else {
- tcg_gen_exit_tb(NULL, 0);
- }
-}
-
-/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
-static void lookup_and_goto_ptr(DisasContext *ctx)
-{
- if (ctx->base.singlestep_enabled) {
- gen_exception_debug();
- } else {
- tcg_gen_lookup_and_goto_ptr();
- }
-}
-
static void gen_exception_illegal(DisasContext *ctx)
{
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
@@ -192,7 +167,7 @@ static void gen_goto_tb(DisasContext *ctx, int n,
target_ulong dest)
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
tcg_gen_movi_tl(cpu_pc, dest);
- lookup_and_goto_ptr(ctx);
+ tcg_gen_lookup_and_goto_ptr();
}
}
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc
b/target/riscv/insn_trans/trans_privileged.c.inc
index a7afcb15ce..75c6ef80a6 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -78,7 +78,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
if (has_ext(ctx, RVS)) {
gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
- exit_tb(ctx); /* no chaining */
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
} else {
return false;
@@ -94,7 +94,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
#ifndef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
- exit_tb(ctx); /* no chaining */
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
#else
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index 920ae0edb3..a6a57c94bb 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -71,9 +71,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
if (a->rd != 0) {
tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
}
-
- /* No chaining with JALR. */
- lookup_and_goto_ptr(ctx);
+ tcg_gen_lookup_and_goto_ptr();
if (misaligned) {
gen_set_label(misaligned);
@@ -421,7 +419,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
* however we need to end the translation block
*/
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- exit_tb(ctx);
+ tcg_gen_exit_tb(NULL, 0);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
@@ -430,7 +428,7 @@ static bool do_csr_post(DisasContext *ctx)
{
/* We may have changed important cpu state -- exit to main loop. */
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- exit_tb(ctx);
+ tcg_gen_exit_tb(NULL, 0);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index fa451938f1..081a5ca34d 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -41,7 +41,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
gen_set_gpr(ctx, a->rd, dst);
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- lookup_and_goto_ptr(ctx);
+ tcg_gen_lookup_and_goto_ptr();
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
--
2.25.1
- [PATCH v2 11/23] target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP, (continued)
- [PATCH v2 11/23] target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP, Richard Henderson, 2021/10/12
- [PATCH v2 13/23] target/mips: Fix single stepping, Richard Henderson, 2021/10/12
- [PATCH v2 15/23] target/openrisc: Drop checks for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 10/23] target/m68k: Drop checks for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 12/23] target/microblaze: Drop checks for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 14/23] target/mips: Drop exit checks for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 17/23] target/riscv: Remove dead code after exception, Richard Henderson, 2021/10/12
- [PATCH v2 18/23] target/riscv: Remove exit_tb and lookup_and_goto_ptr,
Richard Henderson <=
- [PATCH v2 16/23] target/ppc: Drop exit checks for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 21/23] target/sh4: Drop check for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 22/23] target/tricore: Drop check for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 19/23] target/rx: Drop checks for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 20/23] target/s390x: Drop check for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 23/23] target/xtensa: Drop check for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 08/23] target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt, Richard Henderson, 2021/10/12