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[PATCH v4 06/48] target/microblaze: Do not set MO_ALIGN for user-only
From: |
Richard Henderson |
Subject: |
[PATCH v4 06/48] target/microblaze: Do not set MO_ALIGN for user-only |
Date: |
Tue, 12 Oct 2021 19:45:25 -0700 |
The kernel will fix up unaligned accesses, so emulate that
by allowing unaligned accesses to succeed.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/translate.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index a14ffed784..ef44bca2fd 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -727,6 +727,7 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra,
int rb)
}
#endif
+#ifndef CONFIG_USER_ONLY
static void record_unaligned_ess(DisasContext *dc, int rd,
MemOp size, bool store)
{
@@ -739,6 +740,7 @@ static void record_unaligned_ess(DisasContext *dc, int rd,
tcg_set_insn_start_param(dc->insn_start, 1, iflags);
}
+#endif
static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
int mem_index, bool rev)
@@ -760,12 +762,19 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr,
MemOp mop,
}
}
+ /*
+ * For system mode, enforce alignment if the cpu configuration
+ * requires it. For user-mode, the Linux kernel will have fixed up
+ * any unaligned access, so emulate that by *not* setting MO_ALIGN.
+ */
+#ifndef CONFIG_USER_ONLY
if (size > MO_8 &&
(dc->tb_flags & MSR_EE) &&
dc->cfg->unaligned_exceptions) {
record_unaligned_ess(dc, rd, size, false);
mop |= MO_ALIGN;
}
+#endif
tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop);
@@ -906,12 +915,19 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr,
MemOp mop,
}
}
+ /*
+ * For system mode, enforce alignment if the cpu configuration
+ * requires it. For user-mode, the Linux kernel will have fixed up
+ * any unaligned access, so emulate that by *not* setting MO_ALIGN.
+ */
+#ifndef CONFIG_USER_ONLY
if (size > MO_8 &&
(dc->tb_flags & MSR_EE) &&
dc->cfg->unaligned_exceptions) {
record_unaligned_ess(dc, rd, size, true);
mop |= MO_ALIGN;
}
+#endif
tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop);
--
2.25.1
- [PATCH v4 00/48], Richard Henderson, 2021/10/12
- [PATCH v4 03/48] linux-user/alpha: Remove EXCP_UNALIGN handling, Richard Henderson, 2021/10/12
- [PATCH v4 04/48] target/arm: Implement arm_cpu_record_sigbus, Richard Henderson, 2021/10/12
- [PATCH v4 01/48] hw/core: Add TCGCPUOps.record_sigbus, Richard Henderson, 2021/10/12
- [PATCH v4 02/48] linux-user: Add cpu_loop_exit_sigbus, Richard Henderson, 2021/10/12
- [PATCH v4 05/48] linux-user/hppa: Remove EXCP_UNALIGN handling, Richard Henderson, 2021/10/12
- [PATCH v4 06/48] target/microblaze: Do not set MO_ALIGN for user-only,
Richard Henderson <=
- [PATCH v4 11/48] linux-user/hppa: Remove POWERPC_EXCP_ALIGN handling, Richard Henderson, 2021/10/12
- [PATCH v4 12/48] target/sh4: Set fault address in superh_cpu_do_unaligned_access, Richard Henderson, 2021/10/12
- [PATCH v4 07/48] target/ppc: Move SPR_DSISR setting to powerpc_excp, Richard Henderson, 2021/10/12
- [PATCH v4 08/48] target/ppc: Set fault address in ppc_cpu_do_unaligned_access, Richard Henderson, 2021/10/12
- [PATCH v4 09/48] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu, Richard Henderson, 2021/10/12
- [PATCH v4 10/48] target/s390x: Implement s390x_cpu_record_sigbus, Richard Henderson, 2021/10/12
- [PATCH v4 13/48] target/sparc: Remove DEBUG_UNALIGNED, Richard Henderson, 2021/10/12
- [PATCH v4 14/48] target/sparc: Split out build_sfsr, Richard Henderson, 2021/10/12
- [PATCH v4 15/48] target/sparc: Set fault address in sparc_cpu_do_unaligned_access, Richard Henderson, 2021/10/12