While for the DEXTR_S.H opcode:
"The shift argument is provided in the instruction."
For the DEXTRV_S.H opcode we have:
"The five least-significant bits of register rs provide the
shift argument, interpreted as a five-bit unsigned integer;
the remaining bits in rs are ignored."
While 't1' contains the 'rs' register content (the shift value
for DEXTR_S.H), we need to load the value of 'rs' for DEXTRV_S.H.
We can directly use the v1_t TCG register which already contains
this shift value.
Fixes: b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions")
Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
---
target/mips/tcg/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)