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Re: [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 |
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Date: |
Fri, 15 Oct 2021 15:21:29 +1000 |
On Thu, Oct 14, 2021 at 7:08 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> When target_long is 64-bit, we still want a 32-bit bswap for rev8.
> Since this opcode is specific to RV32, we need not conditionalize.
>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index 66dd51de49..c62eea433a 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
> return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
> }
>
> +static void gen_rev8_32(TCGv ret, TCGv src1)
> +{
> + tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
> +}
> +
> static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
> {
> REQUIRE_32BIT(ctx);
> REQUIRE_ZBB(ctx);
> - return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
> + return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
> }
>
> static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
> --
> 2.25.1
>
>
- Re: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, (continued)
- [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/13
- [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/13
- [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64, Richard Henderson, 2021/10/13
- Re: [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64,
Alistair Francis <=
- [PATCH v2 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/13
- [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen, Richard Henderson, 2021/10/13
- [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/13