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[PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing
From: |
frank . chang |
Subject: |
[PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers |
Date: |
Fri, 15 Oct 2021 15:45:12 +0800 |
From: Frank Chang <frank.chang@sifive.com>
If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0fb71875654..688dc1533b6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -48,6 +48,11 @@ static RISCVException fs(CPURISCVState *env, int csrno)
static RISCVException vs(CPURISCVState *env, int csrno)
{
if (env->misa & RVV) {
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+#endif
return RISCV_EXCP_NONE;
}
return RISCV_EXCP_ILLEGAL_INST;
--
2.25.1
- [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support, (continued)
- [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/10/15
- [PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/10/15
- [PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/10/15
- [PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/10/15
- [PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/10/15
- [PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/10/15
- [PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/10/15
- [PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/10/15
- [PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/10/15
- [PATCH v8 12/78] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/10/15
- [PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers,
frank . chang <=
- [PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/10/15
- [PATCH v8 15/78] target/riscv: rvv-1.0: update check functions, frank . chang, 2021/10/15
- [PATCH v8 16/78] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2021/10/15
- [PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions, frank . chang, 2021/10/15
- [PATCH v8 14/78] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/10/15
- [PATCH 18/76] target/riscv: rvv-1.0: configure instructions, frank . chang, 2021/10/15
- [PATCH v8 17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2021/10/15
- [PATCH v8 19/78] target/riscv: rvv-1.0: configure instructions, frank . chang, 2021/10/15
- [PATCH 19/76] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2021/10/15