Re: [PATCH v13 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions

[Richard Henderson]

On 10/15/21 12:29 PM, Alexey Baturo wrote:
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>   target/riscv/insn_trans/trans_rva.c.inc |  3 +++
>   target/riscv/insn_trans/trans_rvd.c.inc |  2 ++
>   target/riscv/insn_trans/trans_rvf.c.inc |  2 ++
>   target/riscv/insn_trans/trans_rvi.c.inc |  2 ++
>   target/riscv/translate.c                | 10 ++++++++++
>   5 files changed, 19 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rva.c.inc 
> b/target/riscv/insn_trans/trans_rva.c.inc
> index 6ea07d89b0..5bdc412191 100644
> --- a/target/riscv/insn_trans/trans_rva.c.inc
> +++ b/target/riscv/insn_trans/trans_rva.c.inc
> @@ -25,6 +25,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp 
> mop)
>       if (a->rl) {
>           tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
>       }
> +    gen_pm_adjust_address(ctx, &src1, src1);
...
> +/*
> + * Temp stub: generates address adjustment for PointerMasking
> + */
> +static void gen_pm_adjust_address(DisasContext *s,
> +                                  TCGv         *dst,
> +                                  TCGv          src)
> +{
> +    tcg_gen_mov_tl(*dst, src);
> +}

I mentioned before that you would not be able to do this.
You are writing to the live cpu register, even if in this case it's a nop.

You could, for example, make the stub be

    *dst = src;

but that begs the question of why not use the return value, and have the stub be

    return src;


r~