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[PATCH v1 4/9] hw/intc: sifive_plic: Cleanup the realize function
From: |
Alistair Francis |
Subject: |
[PATCH v1 4/9] hw/intc: sifive_plic: Cleanup the realize function |
Date: |
Mon, 18 Oct 2021 12:39:26 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 45 +++++++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 21 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index f0e2799efc..d77a5ced23 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -422,35 +422,38 @@ static void sifive_plic_irq_request(void *opaque, int
irq, int level)
static void sifive_plic_realize(DeviceState *dev, Error **errp)
{
- SiFivePLICState *plic = SIFIVE_PLIC(dev);
+ SiFivePLICState *s = SIFIVE_PLIC(dev);
int i;
- memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
- TYPE_SIFIVE_PLIC, plic->aperture_size);
- parse_hart_config(plic);
- plic->bitfield_words = (plic->num_sources + 31) >> 5;
- plic->num_enables = plic->bitfield_words * plic->num_addrs;
- plic->source_priority = g_new0(uint32_t, plic->num_sources);
- plic->target_priority = g_new(uint32_t, plic->num_addrs);
- plic->pending = g_new0(uint32_t, plic->bitfield_words);
- plic->claimed = g_new0(uint32_t, plic->bitfield_words);
- plic->enable = g_new0(uint32_t, plic->num_enables);
- sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
- qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
-
- plic->s_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
- qdev_init_gpio_out(dev, plic->s_external_irqs, plic->num_harts);
-
- plic->m_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
- qdev_init_gpio_out(dev, plic->m_external_irqs, plic->num_harts);
+ memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_plic_ops, s,
+ TYPE_SIFIVE_PLIC, s->aperture_size);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
+
+ parse_hart_config(s);
+
+ s->bitfield_words = (s->num_sources + 31) >> 5;
+ s->num_enables = s->bitfield_words * s->num_addrs;
+ s->source_priority = g_new0(uint32_t, s->num_sources);
+ s->target_priority = g_new(uint32_t, s->num_addrs);
+ s->pending = g_new0(uint32_t, s->bitfield_words);
+ s->claimed = g_new0(uint32_t, s->bitfield_words);
+ s->enable = g_new0(uint32_t, s->num_enables);
+
+ qdev_init_gpio_in(dev, sifive_plic_irq_request, s->num_sources);
+
+ s->s_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
+ qdev_init_gpio_out(dev, s->s_external_irqs, s->num_harts);
+
+ s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
+ qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
/* We can't allow the supervisor to control SEIP as this would allow the
* supervisor to clear a pending external interrupt which will result in
* lost a interrupt in the case a PLIC is attached. The SEIP bit must be
* hardware controlled when a PLIC is attached.
*/
- for (i = 0; i < plic->num_harts; i++) {
- RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(plic->hartid_base + i));
+ for (i = 0; i < s->num_harts; i++) {
+ RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
error_report("SEIP already claimed");
exit(1);
--
2.31.1
- [PATCH v1 1/9] hw/riscv: opentitan: Update to the latest build, Alistair Francis, 2021/10/17
- [PATCH v1 2/9] hw/intc: Remove the Ibex PLIC, Alistair Francis, 2021/10/17
- [PATCH v1 3/9] hw/intc: sifive_plic: Move the properties, Alistair Francis, 2021/10/17
- [PATCH v1 4/9] hw/intc: sifive_plic: Cleanup the realize function,
Alistair Francis <=
- [PATCH v1 5/9] hw/intc: sifive_plic: Cleanup the irq_request function, Alistair Francis, 2021/10/17
- [PATCH v1 6/9] hw/intc: sifive_plic: Add a reset function, Alistair Francis, 2021/10/17
- [PATCH v1 7/9] hw/intc: sifive_plic: Cleanup the write function, Alistair Francis, 2021/10/17
- [PATCH v1 8/9] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2021/10/17