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Re: [PATCH 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineCla
From: |
Igor Mammedov |
Subject: |
Re: [PATCH 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id |
Date: |
Tue, 19 Oct 2021 09:15:10 +0200 |
On Mon, 18 Oct 2021 23:38:27 +0800
Bin Meng <bmeng.cn@gmail.com> wrote:
> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
>
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
same issues as in 2/6
> ---
>
> hw/riscv/sifive_e.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 6e95ea5896..caae860664 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -75,7 +75,6 @@ static void sifive_e_machine_init(MachineState *machine)
>
> SiFiveEState *s = RISCV_E_MACHINE(machine);
> MemoryRegion *sys_mem = get_system_memory();
> - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> int i;
>
> /* Initialize SoC */
> @@ -83,10 +82,8 @@ static void sifive_e_machine_init(MachineState *machine)
> qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
>
> /* Data Tightly Integrated Memory */
> - memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
> - memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
> memory_region_add_subregion(sys_mem,
> - memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
> + memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
>
> /* Mask ROM reset vector */
> uint32_t reset_vec[4];
> @@ -142,6 +139,7 @@ static void sifive_e_machine_class_init(ObjectClass *oc,
> void *data)
> mc->init = sifive_e_machine_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = SIFIVE_E_CPU;
> + mc->default_ram_id = "riscv.sifive.e.ram";
>
> object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
> sifive_e_machine_set_revb);
- [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- Re: [PATCH 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id,
Igor Mammedov <=
- [PATCH 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id, Philippe Mathieu-Daudé, 2021/10/18
- Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id, Igor Mammedov, 2021/10/19