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[PATCH 18/31] hw/intc: Add loongarch ls7a msi interrupt controller suppo
From: |
Xiaojuan Yang |
Subject: |
[PATCH 18/31] hw/intc: Add loongarch ls7a msi interrupt controller support(PCH-MSI) |
Date: |
Tue, 19 Oct 2021 15:35:04 +0800 |
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/intc/Kconfig | 5 ++
hw/intc/loongarch_pch_msi.c | 74 +++++++++++++++++++++++++++++
hw/intc/meson.build | 1 +
hw/loongarch/Kconfig | 1 +
include/hw/intc/loongarch_pch_msi.h | 17 +++++++
5 files changed, 98 insertions(+)
create mode 100644 hw/intc/loongarch_pch_msi.c
create mode 100644 include/hw/intc/loongarch_pch_msi.h
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 3b7eca7b03..c0dc12dfa0 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -77,3 +77,8 @@ config M68K_IRQC
config LOONGARCH_PCH_PIC
bool
select UNIMP
+
+config LOONGARCH_PCH_MSI
+ select MSI_NONBROKEN
+ bool
+ select UNIMP
diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c
new file mode 100644
index 0000000000..78ccabd468
--- /dev/null
+++ b/hw/intc/loongarch_pch_msi.c
@@ -0,0 +1,74 @@
+/*
+ * QEMU Loongson 7A1000 msi interrupt controller.
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/intc/loongarch_pch_msi.h"
+#include "hw/pci/msi.h"
+#include "hw/misc/unimp.h"
+#include "migration/vmstate.h"
+
+#define DEBUG_LOONGARCH_PCH_MSI 0
+
+#define DPRINTF(fmt, ...) \
+do { \
+ if (DEBUG_LOONGARCH_PCH_MSI) { \
+ fprintf(stderr, "LOONGARCH_PCH_MSI: " fmt , ## __VA_ARGS__); \
+ } \
+} while (0)
+
+static uint64_t loongarch_msi_mem_read(void *opaque, hwaddr addr, unsigned
size)
+{
+ return 0;
+}
+
+static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ loongarch_pch_msi *s = opaque;
+ int irq_num = val & 0xff;
+
+ qemu_set_irq(s->pch_msi_irq[irq_num - 32], 1);
+}
+
+static const MemoryRegionOps loongarch_pch_msi_ops = {
+ .read = loongarch_msi_mem_read,
+ .write = loongarch_msi_mem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void loongarch_pch_msi_init(Object *obj)
+{
+ loongarch_pch_msi *s = LOONGARCH_PCH_MSI(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ int tmp;
+
+ memory_region_init_io(&s->msi_mmio, obj, &loongarch_pch_msi_ops,
+ s, TYPE_LOONGARCH_PCH_MSI, 0x8);
+ sysbus_init_mmio(sbd, &s->msi_mmio);
+ msi_nonbroken = true;
+
+ for (tmp = 0; tmp < 224; tmp++) {
+ sysbus_init_irq(sbd, &s->pch_msi_irq[tmp]);
+ }
+}
+
+static const TypeInfo loongarch_pch_msi_info = {
+ .name = TYPE_LOONGARCH_PCH_MSI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(loongarch_pch_msi),
+ .instance_init = loongarch_pch_msi_init,
+};
+
+static void loongarch_pch_msi_register_types(void)
+{
+ type_register_static(&loongarch_pch_msi_info);
+}
+
+type_init(loongarch_pch_msi_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index c61f171d5c..749c27e072 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -59,3 +59,4 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'],
specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.c'))
specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true:
files('loongarch_pch_pic.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true:
files('loongarch_pch_msi.c'))
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index c6d7ebcd5b..4500fd3a57 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -2,3 +2,4 @@ config LOONGSON_3A5000
bool
select PCI_EXPRESS_7A
select LOONGARCH_PCH_PIC
+ select LOONGARCH_PCH_MSI
diff --git a/include/hw/intc/loongarch_pch_msi.h
b/include/hw/intc/loongarch_pch_msi.h
new file mode 100644
index 0000000000..e069663dc8
--- /dev/null
+++ b/include/hw/intc/loongarch_pch_msi.h
@@ -0,0 +1,17 @@
+/*
+ * Loongarch 7A1000 I/O interrupt controller definitions
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+#define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi"
+DECLARE_INSTANCE_CHECKER(struct loongarch_pch_msi, LOONGARCH_PCH_MSI,
+ TYPE_LOONGARCH_PCH_MSI)
+
+typedef struct loongarch_pch_msi {
+ SysBusDevice parent_obj;
+ qemu_irq pch_msi_irq[224];
+ MemoryRegion msi_mmio;
+} loongarch_pch_msi;
--
2.27.0
- [PATCH 03/31] target/loongarch: Set default csr values., (continued)
- [PATCH 03/31] target/loongarch: Set default csr values., Xiaojuan Yang, 2021/10/19
- [PATCH 09/31] target/loongarch: Add other core instructions support, Xiaojuan Yang, 2021/10/19
- [PATCH 10/31] target/loongarch: Add loongarch interrupt and exception handle, Xiaojuan Yang, 2021/10/19
- [PATCH 12/31] target/loongarch: Add timer related instructions support., Xiaojuan Yang, 2021/10/19
- [PATCH 13/31] hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson Platform, Xiaojuan Yang, 2021/10/19
- [PATCH 19/31] hw/intc: Add loongarch extioi interrupt controller(EIOINTC), Xiaojuan Yang, 2021/10/19
- [PATCH 18/31] hw/intc: Add loongarch ls7a msi interrupt controller support(PCH-MSI),
Xiaojuan Yang <=
- [PATCH 17/31] hw/intc: Add loongarch ls7a interrupt controller support(PCH-PIC), Xiaojuan Yang, 2021/10/19
- [PATCH 16/31] hw/loongarch: Add loongarch ipi interrupt support(IPI), Xiaojuan Yang, 2021/10/19
- [PATCH 20/31] hw/loongarch: Add irq hierarchy for the system, Xiaojuan Yang, 2021/10/19
- [PATCH 14/31] hw/loongarch: Add a virt loongarch 3A5000 board support, Xiaojuan Yang, 2021/10/19
- [PATCH 15/31] hw/loongarch: Add loongarch cpu interrupt support(CPUINTC), Xiaojuan Yang, 2021/10/19
- Re: [PATCH 00/31] Add Loongarch softmmu support., WANG Xuerui, 2021/10/19
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