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[PATCH v3 16/21] target/riscv: adding high part of some csrs
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From: |
Frédéric Pétrot |
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Subject: |
[PATCH v3 16/21] target/riscv: adding high part of some csrs |
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Date: |
Tue, 19 Oct 2021 11:48:07 +0200 |
Adding the high part of a minimal set of csr.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8b96ccb37a..27ec4fec63 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -192,6 +192,13 @@ struct CPURISCVState {
target_ulong hgatp;
uint64_t htimedelta;
+ /* Upper 64-bits of 128-bit CSRs */
+ uint64_t mtvech;
+ uint64_t mscratchh;
+ uint64_t mepch;
+ uint64_t satph;
+ uint64_t mstatush;
+
/* Virtual CSRs */
/*
* For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
--
2.33.0
- Re: [PATCH v3 15/21] target/riscv: support for 128-bit M extension, (continued)
- [PATCH v3 20/21] target/riscv: adding 128-bit access functions for some csrs, Frédéric Pétrot, 2021/10/19
- [PATCH v3 21/21] target/riscv: support for 128-bit satp, Frédéric Pétrot, 2021/10/19
- [PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/10/19
- [PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/10/19
- [PATCH v3 16/21] target/riscv: adding high part of some csrs,
Frédéric Pétrot <=
- [PATCH v3 19/21] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/10/19