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Re: [PATCH v5 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump
From: |
Alistair Francis |
Subject: |
Re: [PATCH v5 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump |
Date: |
Wed, 20 Oct 2021 08:12:04 +1000 |
On Wed, Oct 20, 2021 at 2:50 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Use the official debug read interface to the csrs,
> rather than referencing the env slots directly.
> Put the list of csrs to dump into a table.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 90 +++++++++++++++++++++++-----------------------
> 1 file changed, 46 insertions(+), 44 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f352c2b74c..3454b19c17 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -241,52 +241,54 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
> int flags)
> }
> #endif
> qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", "pc", env->pc);
> +
> #ifndef CONFIG_USER_ONLY
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ",
> (target_ulong)env->mstatus);
> - if (riscv_cpu_mxl(env) == MXL_RV32) {
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
> - (target_ulong)(env->mstatus >> 32));
> + {
> + static const int dump_csrs[] = {
> + CSR_MHARTID,
> + CSR_MSTATUS,
> + CSR_MSTATUSH,
> + CSR_HSTATUS,
> + CSR_VSSTATUS,
> + CSR_MIP,
> + CSR_MIE,
> + CSR_MIDELEG,
> + CSR_HIDELEG,
> + CSR_MEDELEG,
> + CSR_HEDELEG,
> + CSR_MTVEC,
> + CSR_STVEC,
> + CSR_VSTVEC,
> + CSR_MEPC,
> + CSR_SEPC,
> + CSR_VSEPC,
> + CSR_MCAUSE,
> + CSR_SCAUSE,
> + CSR_VSCAUSE,
> + CSR_MTVAL,
> + CSR_STVAL,
> + CSR_HTVAL,
> + CSR_MTVAL2,
> + CSR_MSCRATCH,
> + CSR_SSCRATCH,
> + CSR_SATP,
> + };
> +
> + for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
> + int csrno = dump_csrs[i];
> + target_ulong val = 0;
> + RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
> +
> + /*
> + * Rely on the smode, hmode, etc, predicates within csr.c
> + * to do the filtering of the registers that are present.
> + */
> + if (res == RISCV_EXCP_NONE) {
> + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
> + csr_ops[csrno].name, val);
> + }
> + }
> }
> - if (riscv_has_ext(env, RVH)) {
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
> - (target_ulong)env->vsstatus);
> - }
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip);
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
> - if (riscv_has_ext(env, RVH)) {
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
> - }
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
> - if (riscv_has_ext(env, RVH)) {
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
> - }
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec);
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec);
> - if (riscv_has_ext(env, RVH)) {
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec);
> - }
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc);
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc);
> - if (riscv_has_ext(env, RVH)) {
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc);
> - }
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause);
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause);
> - if (riscv_has_ext(env, RVH)) {
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
> - }
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
> - if (riscv_has_ext(env, RVH)) {
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
> - }
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
> - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
> #endif
>
> for (i = 0; i < 32; i++) {
> --
> 2.25.1
>
>
- [PATCH v5 02/16] target/riscv: Create RISCVMXL enumeration, (continued)
- [PATCH v5 02/16] target/riscv: Create RISCVMXL enumeration, Richard Henderson, 2021/10/19
- [PATCH v5 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/19
- [PATCH v5 08/16] target/riscv: Replace is_32bit with get_xl/get_xlen, Richard Henderson, 2021/10/19
- [PATCH v5 03/16] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/19
- [PATCH v5 06/16] target/riscv: Use REQUIRE_64BIT in amo_check64, Richard Henderson, 2021/10/19
- [PATCH v5 04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/19
- [PATCH v5 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson, 2021/10/19
- [PATCH v5 10/16] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/19
- [PATCH v5 07/16] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/19
- [PATCH v5 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump, Richard Henderson, 2021/10/19
- Re: [PATCH v5 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump,
Alistair Francis <=
- [PATCH v5 16/16] target/riscv: Compute mstatus.sd on demand, Richard Henderson, 2021/10/19
- [PATCH v5 14/16] target/riscv: Align gprs and fprs in cpu_dump, Richard Henderson, 2021/10/19
- [PATCH v5 11/16] target/riscv: Adjust trans_rev8_32 for riscv64, Richard Henderson, 2021/10/19
- [PATCH v5 13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/19
- [PATCH v5 12/16] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/19