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[PULL 14/33] target/riscv: Properly check SEW in amo_op
From: |
Alistair Francis |
Subject: |
[PULL 14/33] target/riscv: Properly check SEW in amo_op |
Date: |
Fri, 22 Oct 2021 23:37:53 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
We're currently assuming SEW <= 3, and the "else" from
the SEW == 3 must be less. Use a switch and explicitly
bound both SEW and SEQ for all cases.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-8-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 26 +++++++++++++------------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 233131bae1..17ee3babef 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -704,18 +704,20 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t
seq)
gen_helper_exit_atomic(cpu_env);
s->base.is_jmp = DISAS_NORETURN;
return true;
- } else {
- if (s->sew == 3) {
- if (!is_32bit(s)) {
- fn = fnsd[seq];
- } else {
- /* Check done in amo_check(). */
- g_assert_not_reached();
- }
- } else {
- assert(seq < ARRAY_SIZE(fnsw));
- fn = fnsw[seq];
- }
+ }
+
+ switch (s->sew) {
+ case 0 ... 2:
+ assert(seq < ARRAY_SIZE(fnsw));
+ fn = fnsw[seq];
+ break;
+ case 3:
+ /* XLEN check done in amo_check(). */
+ assert(seq < ARRAY_SIZE(fnsd));
+ fn = fnsd[seq];
+ break;
+ default:
+ g_assert_not_reached();
}
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
--
2.31.1
- [PULL 04/33] hw/riscv: virt: Use machine->ram as the system memory, (continued)
- [PULL 04/33] hw/riscv: virt: Use machine->ram as the system memory, Alistair Francis, 2021/10/22
- [PULL 05/33] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh, Alistair Francis, 2021/10/22
- [PULL 06/33] target/riscv: Remove some unused macros, Alistair Francis, 2021/10/22
- [PULL 07/33] target/riscv: Organise the CPU properties, Alistair Francis, 2021/10/22
- [PULL 08/33] target/riscv: Move cpu_get_tb_cpu_state out of line, Alistair Francis, 2021/10/22
- [PULL 09/33] target/riscv: Create RISCVMXL enumeration, Alistair Francis, 2021/10/22
- [PULL 10/33] target/riscv: Split misa.mxl and misa.ext, Alistair Francis, 2021/10/22
- [PULL 12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Alistair Francis, 2021/10/22
- [PULL 11/33] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Alistair Francis, 2021/10/22
- [PULL 13/33] target/riscv: Use REQUIRE_64BIT in amo_check64, Alistair Francis, 2021/10/22
- [PULL 14/33] target/riscv: Properly check SEW in amo_op,
Alistair Francis <=
- [PULL 15/33] target/riscv: Replace is_32bit with get_xl/get_xlen, Alistair Francis, 2021/10/22
- [PULL 16/33] target/riscv: Replace DisasContext.w with DisasContext.ol, Alistair Francis, 2021/10/22
- [PULL 17/33] target/riscv: Use gen_arith_per_ol for RVM, Alistair Francis, 2021/10/22
- [PULL 18/33] target/riscv: Adjust trans_rev8_32 for riscv64, Alistair Francis, 2021/10/22
- [PULL 19/33] target/riscv: Use gen_unary_per_ol for RVB, Alistair Francis, 2021/10/22
- [PULL 20/33] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Alistair Francis, 2021/10/22
- [PULL 22/33] target/riscv: Compute mstatus.sd on demand, Alistair Francis, 2021/10/22
- [PULL 21/33] target/riscv: Use riscv_csrrw_debug for cpu_dump, Alistair Francis, 2021/10/22
- [PULL 23/33] hw/riscv: opentitan: Update to the latest build, Alistair Francis, 2021/10/22
- [PULL 25/33] hw/intc: sifive_plic: Move the properties, Alistair Francis, 2021/10/22