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[PULL 18/33] target/riscv: Adjust trans_rev8_32 for riscv64
From: |
Alistair Francis |
Subject: |
[PULL 18/33] target/riscv: Adjust trans_rev8_32 for riscv64 |
Date: |
Fri, 22 Oct 2021 23:37:57 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-12-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 9ef8ab94ad..d6f9e9fc83 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
}
+static void gen_rev8_32(TCGv ret, TCGv src1)
+{
+ tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
+}
+
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
REQUIRE_32BIT(ctx);
REQUIRE_ZBB(ctx);
- return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
+ return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
}
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
--
2.31.1
- [PULL 08/33] target/riscv: Move cpu_get_tb_cpu_state out of line, (continued)
- [PULL 08/33] target/riscv: Move cpu_get_tb_cpu_state out of line, Alistair Francis, 2021/10/22
- [PULL 09/33] target/riscv: Create RISCVMXL enumeration, Alistair Francis, 2021/10/22
- [PULL 10/33] target/riscv: Split misa.mxl and misa.ext, Alistair Francis, 2021/10/22
- [PULL 12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Alistair Francis, 2021/10/22
- [PULL 11/33] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Alistair Francis, 2021/10/22
- [PULL 13/33] target/riscv: Use REQUIRE_64BIT in amo_check64, Alistair Francis, 2021/10/22
- [PULL 14/33] target/riscv: Properly check SEW in amo_op, Alistair Francis, 2021/10/22
- [PULL 15/33] target/riscv: Replace is_32bit with get_xl/get_xlen, Alistair Francis, 2021/10/22
- [PULL 16/33] target/riscv: Replace DisasContext.w with DisasContext.ol, Alistair Francis, 2021/10/22
- [PULL 17/33] target/riscv: Use gen_arith_per_ol for RVM, Alistair Francis, 2021/10/22
- [PULL 18/33] target/riscv: Adjust trans_rev8_32 for riscv64,
Alistair Francis <=
- [PULL 19/33] target/riscv: Use gen_unary_per_ol for RVB, Alistair Francis, 2021/10/22
- [PULL 20/33] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Alistair Francis, 2021/10/22
- [PULL 22/33] target/riscv: Compute mstatus.sd on demand, Alistair Francis, 2021/10/22
- [PULL 21/33] target/riscv: Use riscv_csrrw_debug for cpu_dump, Alistair Francis, 2021/10/22
- [PULL 23/33] hw/riscv: opentitan: Update to the latest build, Alistair Francis, 2021/10/22
- [PULL 25/33] hw/intc: sifive_plic: Move the properties, Alistair Francis, 2021/10/22
- [PULL 26/33] hw/intc: sifive_plic: Cleanup the realize function, Alistair Francis, 2021/10/22
- [PULL 30/33] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id, Alistair Francis, 2021/10/22
- [PULL 29/33] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id, Alistair Francis, 2021/10/22
- [PULL 27/33] hw/intc: sifive_plic: Cleanup the irq_request function, Alistair Francis, 2021/10/22