[PATCH 0/3] target/mips: MSA opcode fixes

[Philippe Mathieu-Daudé]

Fix a pair of MSA opcodes, and update the MSA_IR config register
in the Loongson-3A4000 model.

Philippe Mathieu-Daudé (3):
  target/mips: Fix MSA MADDV.B opcode
  target/mips: Fix MSA MSUBV.B opcode
  target/mips: Fix Loongson-3A4000 MSAIR config register

 target/mips/tcg/msa_helper.c | 64 ++++++++++++++++++------------------
 target/mips/cpu-defs.c.inc   |  1 +
 2 files changed, 33 insertions(+), 32 deletions(-)

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2.31.1